This is a note to let you know that I've just added the patch titled PCI: aardvark: Set PCI Bridge Class Code to PCI Bridge to the 5.15-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: pci-aardvark-set-pci-bridge-class-code-to-pci-bridge.patch and it can be found in the queue-5.15 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let <stable@xxxxxxxxxxxxxxx> know about it. >From 84e1b4045dc887b78bdc87d92927093dc3a465aa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@xxxxxxxxxx> Date: Thu, 28 Oct 2021 20:56:57 +0200 Subject: PCI: aardvark: Set PCI Bridge Class Code to PCI Bridge MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Pali Rohár <pali@xxxxxxxxxx> commit 84e1b4045dc887b78bdc87d92927093dc3a465aa upstream. Aardvark controller has something like config space of a Root Port available at offset 0x0 of internal registers - these registers are used for implementation of the emulated bridge. The default value of Class Code of this bridge corresponds to a RAID Mass storage controller, though. (This is probably intended for when the controller is used as Endpoint.) Change the Class Code to correspond to a PCI Bridge. Add comment explaining this change. Link: https://lore.kernel.org/r/20211028185659.20329-6-kabel@xxxxxxxxxx Fixes: 8a3ebd8de328 ("PCI: aardvark: Implement emulated root PCI bridge config space") Signed-off-by: Pali Rohár <pali@xxxxxxxxxx> Signed-off-by: Marek Behún <kabel@xxxxxxxxxx> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx> Cc: stable@xxxxxxxxxxxxxxx Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> --- drivers/pci/controller/pci-aardvark.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -560,6 +560,26 @@ static void advk_pcie_setup_hw(struct ad reg = (PCI_VENDOR_ID_MARVELL << 16) | PCI_VENDOR_ID_MARVELL; advk_writel(pcie, reg, VENDOR_ID_REG); + /* + * Change Class Code of PCI Bridge device to PCI Bridge (0x600400), + * because the default value is Mass storage controller (0x010400). + * + * Note that this Aardvark PCI Bridge does not have compliant Type 1 + * Configuration Space and it even cannot be accessed via Aardvark's + * PCI config space access method. Something like config space is + * available in internal Aardvark registers starting at offset 0x0 + * and is reported as Type 0. In range 0x10 - 0x34 it has totally + * different registers. + * + * Therefore driver uses emulation of PCI Bridge which emulates + * access to configuration space via internal Aardvark registers or + * emulated configuration buffer. + */ + reg = advk_readl(pcie, PCIE_CORE_DEV_REV_REG); + reg &= ~0xffffff00; + reg |= (PCI_CLASS_BRIDGE_PCI << 8) << 8; + advk_writel(pcie, reg, PCIE_CORE_DEV_REV_REG); + /* Disable Root Bridge I/O space, memory space and bus mastering */ reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); reg &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); Patches currently in stable-queue which might be from pali@xxxxxxxxxx are queue-5.15/pci-aardvark-fix-reporting-data-link-layer-link-active.patch queue-5.15/pci-aardvark-fix-configuring-reference-clock.patch queue-5.15/pci-aardvark-fix-support-for-bus-mastering-and-pci_command-on-emulated-bridge.patch queue-5.15/pci-mark-atheros-qca6174-to-avoid-bus-reset.patch queue-5.15/serial-core-fix-initializing-and-restoring-termios-speed.patch queue-5.15/pci-pci-bridge-emul-fix-emulation-of-w1c-bits.patch queue-5.15/pci-aardvark-fix-support-for-pci_bridge_ctl_bus_reset-on-emulated-bridge.patch queue-5.15/pci-aardvark-fix-checking-for-link-up-via-ltssm-state.patch queue-5.15/pci-aardvark-fix-return-value-of-msi-domain-.alloc-method.patch queue-5.15/pci-aardvark-read-all-16-bits-from-pcie_msi_payload_reg.patch queue-5.15/pci-aardvark-do-not-unmask-unused-interrupts.patch queue-5.15/pci-aardvark-do-not-clear-status-bits-of-masked-interrupts.patch queue-5.15/pci-aardvark-set-pci-bridge-class-code-to-pci-bridge.patch queue-5.15/pci-aardvark-fix-support-for-pci_rom_address1-on-emulated-bridge.patch