This is a note to let you know that I've just added the patch titled PCI: aardvark: Fix support for PCI_ROM_ADDRESS1 on emulated bridge to the 5.14-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: pci-aardvark-fix-support-for-pci_rom_address1-on-emulated-bridge.patch and it can be found in the queue-5.14 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let <stable@xxxxxxxxxxxxxxx> know about it. >From 239edf686c14a9ff926dec2f350289ed7adfefe2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@xxxxxxxxxx> Date: Thu, 28 Oct 2021 20:56:59 +0200 Subject: PCI: aardvark: Fix support for PCI_ROM_ADDRESS1 on emulated bridge MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Pali Rohár <pali@xxxxxxxxxx> commit 239edf686c14a9ff926dec2f350289ed7adfefe2 upstream. This register is exported at address offset 0x30. Link: https://lore.kernel.org/r/20211028185659.20329-8-kabel@xxxxxxxxxx Fixes: 8a3ebd8de328 ("PCI: aardvark: Implement emulated root PCI bridge config space") Signed-off-by: Pali Rohár <pali@xxxxxxxxxx> Signed-off-by: Marek Behún <kabel@xxxxxxxxxx> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx> Cc: stable@xxxxxxxxxxxxxxx Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> --- drivers/pci/controller/pci-aardvark.c | 9 +++++++++ 1 file changed, 9 insertions(+) --- a/drivers/pci/controller/pci-aardvark.c +++ b/drivers/pci/controller/pci-aardvark.c @@ -32,6 +32,7 @@ #define PCIE_CORE_DEV_ID_REG 0x0 #define PCIE_CORE_CMD_STATUS_REG 0x4 #define PCIE_CORE_DEV_REV_REG 0x8 +#define PCIE_CORE_EXP_ROM_BAR_REG 0x30 #define PCIE_CORE_PCIEXP_CAP 0xc0 #define PCIE_CORE_ERR_CAPCTL_REG 0x118 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX BIT(5) @@ -813,6 +814,10 @@ advk_pci_bridge_emul_base_conf_read(stru *value = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); return PCI_BRIDGE_EMUL_HANDLED; + case PCI_ROM_ADDRESS1: + *value = advk_readl(pcie, PCIE_CORE_EXP_ROM_BAR_REG); + return PCI_BRIDGE_EMUL_HANDLED; + case PCI_INTERRUPT_LINE: { /* * From the whole 32bit register we support reading from HW only @@ -845,6 +850,10 @@ advk_pci_bridge_emul_base_conf_write(str advk_writel(pcie, new, PCIE_CORE_CMD_STATUS_REG); break; + case PCI_ROM_ADDRESS1: + advk_writel(pcie, new, PCIE_CORE_EXP_ROM_BAR_REG); + break; + case PCI_INTERRUPT_LINE: if (mask & (PCI_BRIDGE_CTL_BUS_RESET << 16)) { u32 val = advk_readl(pcie, PCIE_CORE_CTRL1_REG); Patches currently in stable-queue which might be from pali@xxxxxxxxxx are queue-5.14/pci-aardvark-fix-reporting-data-link-layer-link-active.patch queue-5.14/pci-aardvark-fix-configuring-reference-clock.patch queue-5.14/pci-aardvark-fix-support-for-bus-mastering-and-pci_command-on-emulated-bridge.patch queue-5.14/pci-mark-atheros-qca6174-to-avoid-bus-reset.patch queue-5.14/serial-core-fix-initializing-and-restoring-termios-speed.patch queue-5.14/pci-pci-bridge-emul-fix-emulation-of-w1c-bits.patch queue-5.14/pci-aardvark-fix-support-for-pci_bridge_ctl_bus_reset-on-emulated-bridge.patch queue-5.14/pci-aardvark-fix-checking-for-link-up-via-ltssm-state.patch queue-5.14/pci-aardvark-fix-return-value-of-msi-domain-.alloc-method.patch queue-5.14/pci-aardvark-read-all-16-bits-from-pcie_msi_payload_reg.patch queue-5.14/pci-aardvark-do-not-unmask-unused-interrupts.patch queue-5.14/pci-aardvark-do-not-clear-status-bits-of-masked-interrupts.patch queue-5.14/pci-aardvark-set-pci-bridge-class-code-to-pci-bridge.patch queue-5.14/pci-aardvark-fix-support-for-pci_rom_address1-on-emulated-bridge.patch