This is a note to let you know that I've just added the patch titled
PCI: aardvark: Fix configuring Reference clock
to the 5.10-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
pci-aardvark-fix-configuring-reference-clock.patch
and it can be found in the queue-5.10 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From 46ef6090dbf590711cb12680b6eafde5fa21fe87 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@xxxxxxxxxx>
Date: Tue, 5 Oct 2021 20:09:44 +0200
Subject: PCI: aardvark: Fix configuring Reference clock
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From: Pali Rohár <pali@xxxxxxxxxx>
commit 46ef6090dbf590711cb12680b6eafde5fa21fe87 upstream.
Commit 366697018c9a ("PCI: aardvark: Add PHY support") introduced
configuration of PCIe Reference clock via PCIE_CORE_REF_CLK_REG register,
but did it incorrectly.
PCIe Reference clock differential pair is routed from system board to
endpoint card, so on CPU side it has output direction. Therefore it is
required to enable transmitting and disable receiving.
Default configuration according to Armada 3700 Functional Specifications is
enabled receiver part and disabled transmitter.
We need this change because otherwise PCIe Reference clock is configured to
some undefined state when differential pair is used for both transmitting
and receiving.
Fix this by disabling receiver part.
Link: https://lore.kernel.org/r/20211005180952.6812-6-kabel@xxxxxxxxxx
Fixes: 366697018c9a ("PCI: aardvark: Add PHY support")
Signed-off-by: Pali Rohár <pali@xxxxxxxxxx>
Signed-off-by: Marek Behún <kabel@xxxxxxxxxx>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx>
Reviewed-by: Marek Behún <kabel@xxxxxxxxxx>
Cc: stable@xxxxxxxxxxxxxxx
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
drivers/pci/controller/pci-aardvark.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -98,6 +98,7 @@
#define PCIE_CORE_CTRL2_MSI_ENABLE BIT(10)
#define PCIE_CORE_REF_CLK_REG (CONTROL_BASE_ADDR + 0x14)
#define PCIE_CORE_REF_CLK_TX_ENABLE BIT(1)
+#define PCIE_CORE_REF_CLK_RX_ENABLE BIT(2)
#define PCIE_MSG_LOG_REG (CONTROL_BASE_ADDR + 0x30)
#define PCIE_ISR0_REG (CONTROL_BASE_ADDR + 0x40)
#define PCIE_MSG_PM_PME_MASK BIT(7)
@@ -529,9 +530,15 @@ static void advk_pcie_setup_hw(struct ad
u32 reg;
int i;
- /* Enable TX */
+ /*
+ * Configure PCIe Reference clock. Direction is from the PCIe
+ * controller to the endpoint card, so enable transmitting of
+ * Reference clock differential signal off-chip and disable
+ * receiving off-chip differential signal.
+ */
reg = advk_readl(pcie, PCIE_CORE_REF_CLK_REG);
reg |= PCIE_CORE_REF_CLK_TX_ENABLE;
+ reg &= ~PCIE_CORE_REF_CLK_RX_ENABLE;
advk_writel(pcie, reg, PCIE_CORE_REF_CLK_REG);
/* Set to Direct mode */
Patches currently in stable-queue which might be from pali@xxxxxxxxxx are
queue-5.10/pci-aardvark-fix-reporting-data-link-layer-link-active.patch
queue-5.10/pci-aardvark-fix-configuring-reference-clock.patch
queue-5.10/pci-aardvark-fix-support-for-bus-mastering-and-pci_command-on-emulated-bridge.patch
queue-5.10/pci-mark-atheros-qca6174-to-avoid-bus-reset.patch
queue-5.10/serial-core-fix-initializing-and-restoring-termios-speed.patch
queue-5.10/pci-pci-bridge-emul-fix-emulation-of-w1c-bits.patch
queue-5.10/pci-aardvark-fix-support-for-pci_bridge_ctl_bus_reset-on-emulated-bridge.patch
queue-5.10/pci-aardvark-fix-checking-for-link-up-via-ltssm-state.patch
queue-5.10/pci-aardvark-fix-return-value-of-msi-domain-.alloc-method.patch
queue-5.10/pci-aardvark-read-all-16-bits-from-pcie_msi_payload_reg.patch
queue-5.10/pci-aardvark-do-not-unmask-unused-interrupts.patch
queue-5.10/pci-aardvark-do-not-clear-status-bits-of-masked-interrupts.patch
queue-5.10/pci-aardvark-set-pci-bridge-class-code-to-pci-bridge.patch
queue-5.10/pci-aardvark-fix-support-for-pci_rom_address1-on-emulated-bridge.patch
