This is a note to let you know that I've just added the patch titled
riscv: fix misalgned trap vector base address
to the 5.14-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
riscv-fix-misalgned-trap-vector-base-address.patch
and it can be found in the queue-5.14 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.
>From 64a19591a2938b170aa736443d5d3bf4c51e1388 Mon Sep 17 00:00:00 2001
From: Chen Lu <181250012@xxxxxxxxxxxxxxxx>
Date: Mon, 18 Oct 2021 13:22:38 +0800
Subject: riscv: fix misalgned trap vector base address
From: Chen Lu <181250012@xxxxxxxxxxxxxxxx>
commit 64a19591a2938b170aa736443d5d3bf4c51e1388 upstream.
The trap vector marked by label .Lsecondary_park must align on a
4-byte boundary, as the {m,s}tvec is defined to require 4-byte
alignment.
Signed-off-by: Chen Lu <181250012@xxxxxxxxxxxxxxxx>
Reviewed-by: Anup Patel <anup.patel@xxxxxxx>
Fixes: e011995e826f ("RISC-V: Move relocate and few other functions out of __init")
Cc: stable@xxxxxxxxxxxxxxx
Signed-off-by: Palmer Dabbelt <palmerdabbelt@xxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx>
---
arch/riscv/kernel/head.S | 1 +
1 file changed, 1 insertion(+)
--- a/arch/riscv/kernel/head.S
+++ b/arch/riscv/kernel/head.S
@@ -193,6 +193,7 @@ setup_trap_vector:
csrw CSR_SCRATCH, zero
ret
+.align 2
.Lsecondary_park:
/* We lack SMP support or have too many harts, so park this hart */
wfi
Patches currently in stable-queue which might be from 181250012@xxxxxxxxxxxxxxxx are
queue-5.14/riscv-fix-misalgned-trap-vector-base-address.patch
