This is a note to let you know that I've just added the patch titled clk: socfpga: agilex: add the bypass register for s2f_usr0 clock to the 5.10-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: clk-socfpga-agilex-add-the-bypass-register-for-s2f_usr0-clock.patch and it can be found in the queue-5.10 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let <stable@xxxxxxxxxxxxxxx> know about it. >From d17929eb1066d1c1653aae9bb4396a9f1d6602ac Mon Sep 17 00:00:00 2001 From: Dinh Nguyen <dinguyen@xxxxxxxxxx> Date: Tue, 13 Jul 2021 09:46:21 -0500 Subject: clk: socfpga: agilex: add the bypass register for s2f_usr0 clock From: Dinh Nguyen <dinguyen@xxxxxxxxxx> commit d17929eb1066d1c1653aae9bb4396a9f1d6602ac upstream. Add the bypass register for the s2f_user0_clk. Fixes: 80c6b7a0894f ("clk: socfpga: agilex: add clock driver for the Agilex platform") Cc: stable@xxxxxxxxxxxxxxx Signed-off-by: Kris Chaplin <kris.chaplin@xxxxxxxxx> Signed-off-by: Dinh Nguyen <dinguyen@xxxxxxxxxx> Link: https://lore.kernel.org/r/20210713144621.605140-3-dinguyen@xxxxxxxxxx Signed-off-by: Stephen Boyd <sboyd@xxxxxxxxxx> Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> --- drivers/clk/socfpga/clk-agilex.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/drivers/clk/socfpga/clk-agilex.c +++ b/drivers/clk/socfpga/clk-agilex.c @@ -267,7 +267,7 @@ static const struct stratix10_perip_cnt_ { AGILEX_SDMMC_FREE_CLK, "sdmmc_free_clk", NULL, sdmmc_free_mux, ARRAY_SIZE(sdmmc_free_mux), 0, 0xE4, 0, 0, 0}, { AGILEX_S2F_USER0_FREE_CLK, "s2f_user0_free_clk", NULL, s2f_usr0_free_mux, - ARRAY_SIZE(s2f_usr0_free_mux), 0, 0xE8, 0, 0, 0}, + ARRAY_SIZE(s2f_usr0_free_mux), 0, 0xE8, 0, 0x30, 2}, { AGILEX_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL, s2f_usr1_free_mux, ARRAY_SIZE(s2f_usr1_free_mux), 0, 0xEC, 0, 0x88, 5}, { AGILEX_PSI_REF_FREE_CLK, "psi_ref_free_clk", NULL, psi_ref_free_mux, Patches currently in stable-queue which might be from dinguyen@xxxxxxxxxx are queue-5.10/clk-socfpga-agilex-fix-up-s2f_user0_clk-representation.patch queue-5.10/clk-socfpga-agilex-fix-the-parents-of-the-psi_ref_clk.patch queue-5.10/clk-socfpga-agilex-add-the-bypass-register-for-s2f_usr0-clock.patch