Patch "arm64: dts: ti: k3-j721e-common-proc-board: Use external clock for SERDES" has been added to the 5.13-stable tree

[Sasha Levin <sashal@xxxxxxxxxx>]

This is a note to let you know that I've just added the patch titled

    arm64: dts: ti: k3-j721e-common-proc-board: Use external clock for SERDES

to the 5.13-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     arm64-dts-ti-k3-j721e-common-proc-board-use-external.patch
and it can be found in the queue-5.13 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 470e3b60854c1db89ab84cec705cbb29ba840c1e
Author: Kishon Vijay Abraham I <kishon@xxxxxx>
Date:   Thu Jun 3 20:04:26 2021 +0530

    arm64: dts: ti: k3-j721e-common-proc-board: Use external clock for SERDES
    
    [ Upstream commit f2a7657ad7a821de9cc77d071a5587b243144cd5 ]
    
    Use external clock for all the SERDES used by PCIe controller. This will
    make the same clock used by the local SERDES as well as the clock
    provided to the PCIe connector.
    
    Signed-off-by: Kishon Vijay Abraham I <kishon@xxxxxx>
    Reviewed-by: Aswath Govindraju <a-govindraju@xxxxxx>
    Signed-off-by: Nishanth Menon <nm@xxxxxx>
    Link: https://lore.kernel.org/r/20210603143427.28735-4-kishon@xxxxxx
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 86f7ab511ee8..1b25a5ae9635 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -9,6 +9,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/input/input.h>
 #include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy-cadence.h>
 
 / {
 	chosen {
@@ -639,7 +640,40 @@
 	clock-frequency = <100000000>;
 };
 
+&wiz0_pll1_refclk {
+	assigned-clocks = <&wiz0_pll1_refclk>;
+	assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz0_refclk_dig {
+	assigned-clocks = <&wiz0_refclk_dig>;
+	assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz1_pll1_refclk {
+	assigned-clocks = <&wiz1_pll1_refclk>;
+	assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz1_refclk_dig {
+	assigned-clocks = <&wiz1_refclk_dig>;
+	assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz2_pll1_refclk {
+	assigned-clocks = <&wiz2_pll1_refclk>;
+	assigned-clock-parents = <&cmn_refclk1>;
+};
+
+&wiz2_refclk_dig {
+	assigned-clocks = <&wiz2_refclk_dig>;
+	assigned-clock-parents = <&cmn_refclk1>;
+};
+
 &serdes0 {
+	assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
+	assigned-clock-parents = <&wiz0_pll1_refclk>;
+
 	serdes0_pcie_link: link@0 {
 		reg = <0>;
 		cdns,num-lanes = <1>;
@@ -650,6 +684,9 @@
 };
 
 &serdes1 {
+	assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>;
+	assigned-clock-parents = <&wiz1_pll1_refclk>;
+
 	serdes1_pcie_link: link@0 {
 		reg = <0>;
 		cdns,num-lanes = <2>;
@@ -660,6 +697,9 @@
 };
 
 &serdes2 {
+	assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>;
+	assigned-clock-parents = <&wiz2_pll1_refclk>;
+
 	serdes2_pcie_link: link@0 {
 		reg = <0>;
 		cdns,num-lanes = <2>;