This is a note to let you know that I've just added the patch titled drm/amdgpu: fix the hang caused by PCIe link width switch to the 5.13-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: drm-amdgpu-fix-the-hang-caused-by-pcie-link-width-switch.patch and it can be found in the queue-5.13 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let <stable@xxxxxxxxxxxxxxx> know about it. >From adcf949e664a8b04df2fb8aa916892e58561653c Mon Sep 17 00:00:00 2001 From: Evan Quan <evan.quan@xxxxxxx> Date: Tue, 25 May 2021 14:36:29 +0800 Subject: drm/amdgpu: fix the hang caused by PCIe link width switch From: Evan Quan <evan.quan@xxxxxxx> commit adcf949e664a8b04df2fb8aa916892e58561653c upstream. SMU had set all the necessary fields for a link width switch but the width switch wasn't occurring because the link was idle in the L1 state. Setting LC_L1_RECONFIG_EN=0x1 will allow width switches to also be initiated while in L1 instead of waiting until the link is back in L0. Signed-off-by: Evan Quan <evan.quan@xxxxxxx> Reviewed-by: Lijo Lazar <lijo.lazar@xxxxxxx> Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx> Cc: stable@xxxxxxxxxxxxxxx Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> --- drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h | 1 + drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 13 +++++++++++++ drivers/gpu/drm/amd/amdgpu/nv.c | 3 +++ 3 files changed, 17 insertions(+) --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h @@ -94,6 +94,7 @@ struct amdgpu_nbio_funcs { bool enable); void (*program_aspm)(struct amdgpu_device *adev); void (*apply_lc_spc_mode_wa)(struct amdgpu_device *adev); + void (*apply_l1_link_width_reconfig_wa)(struct amdgpu_device *adev); }; struct amdgpu_nbio { --- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c @@ -490,6 +490,18 @@ static void nbio_v2_3_apply_lc_spc_mode_ } } +static void nbio_v2_3_apply_l1_link_width_reconfig_wa(struct amdgpu_device *adev) +{ + uint32_t reg_data = 0; + + if (adev->asic_type != CHIP_NAVI10) + return; + + reg_data = RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL); + reg_data |= PCIE_LC_LINK_WIDTH_CNTL__LC_L1_RECONFIG_EN_MASK; + WREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL, reg_data); +} + const struct amdgpu_nbio_funcs nbio_v2_3_funcs = { .get_hdp_flush_req_offset = nbio_v2_3_get_hdp_flush_req_offset, .get_hdp_flush_done_offset = nbio_v2_3_get_hdp_flush_done_offset, @@ -512,4 +524,5 @@ const struct amdgpu_nbio_funcs nbio_v2_3 .enable_aspm = nbio_v2_3_enable_aspm, .program_aspm = nbio_v2_3_program_aspm, .apply_lc_spc_mode_wa = nbio_v2_3_apply_lc_spc_mode_wa, + .apply_l1_link_width_reconfig_wa = nbio_v2_3_apply_l1_link_width_reconfig_wa, }; --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -1197,6 +1197,9 @@ static int nv_common_hw_init(void *handl if (adev->nbio.funcs->apply_lc_spc_mode_wa) adev->nbio.funcs->apply_lc_spc_mode_wa(adev); + if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa) + adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev); + /* enable pcie gen2/3 link */ nv_pcie_gen3_enable(adev); /* enable aspm */ Patches currently in stable-queue which might be from evan.quan@xxxxxxx are queue-5.13/drm-amdgpu-fix-nak-g-generation-during-pci-e-link-width-switch.patch queue-5.13/drm-amd-display-fix-incorrrect-valid-irq-check.patch queue-5.13/drm-amdgpu-fix-the-hang-caused-by-pcie-link-width-switch.patch