This is a note to let you know that I've just added the patch titled riscv: dts: fu740: fix cache-controller interrupts to the 5.12-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: riscv-dts-fu740-fix-cache-controller-interrupts.patch and it can be found in the queue-5.12 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let <stable@xxxxxxxxxxxxxxx> know about it. commit 88108a67f70e5a37ed107c7e12902f53b2fe7286 Author: David Abdurachmanov <david.abdurachmanov@xxxxxxxxxx> Date: Sat Jun 12 17:43:57 2021 -0700 riscv: dts: fu740: fix cache-controller interrupts [ Upstream commit 7ede12b01b59dc67bef2e2035297dd2da5bfe427 ] The order of interrupt numbers is incorrect. The order for FU740 is: DirError, DataError, DataFail, DirFail From SiFive FU740-C000 Manual: 19 - L2 Cache DirError 20 - L2 Cache DirFail 21 - L2 Cache DataError 22 - L2 Cache DataFail Signed-off-by: David Abdurachmanov <david.abdurachmanov@xxxxxxxxxx> Signed-off-by: Palmer Dabbelt <palmerdabbelt@xxxxxxxxxx> Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx> diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi index eeb4f8c3e0e7..d0d206cdb999 100644 --- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi +++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi @@ -272,7 +272,7 @@ ccache: cache-controller@2010000 { cache-size = <2097152>; cache-unified; interrupt-parent = <&plic0>; - interrupts = <19 20 21 22>; + interrupts = <19 21 22 20>; reg = <0x0 0x2010000 0x0 0x1000>; }; gpio: gpio@10060000 {