Patch "PCI: Add AMD RS690 quirk to enable 64-bit DMA" has been added to the 5.12-stable tree

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This is a note to let you know that I've just added the patch titled

    PCI: Add AMD RS690 quirk to enable 64-bit DMA

to the 5.12-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     pci-add-amd-rs690-quirk-to-enable-64-bit-dma.patch
and it can be found in the queue-5.12 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 9a45ae5504b7201332735adaa07439ef2e8598d6
Author: Mikel Rychliski <mikel@xxxxxxxxxx>
Date:   Fri Jun 11 17:48:23 2021 -0400

    PCI: Add AMD RS690 quirk to enable 64-bit DMA
    
    [ Upstream commit cacf994a91d3a55c0c2f853d6429cd7b86113915 ]
    
    Although the AMD RS690 chipset has 64-bit DMA support, BIOS implementations
    sometimes fail to configure the memory limit registers correctly.
    
    The Acer F690GVM mainboard uses this chipset and a Marvell 88E8056 NIC. The
    sky2 driver programs the NIC to use 64-bit DMA, which will not work:
    
      sky2 0000:02:00.0: error interrupt status=0x8
      sky2 0000:02:00.0 eth0: tx timeout
      sky2 0000:02:00.0 eth0: transmit ring 0 .. 22 report=0 done=0
    
    Other drivers required by this mainboard either don't support 64-bit DMA,
    or have it disabled using driver specific quirks. For example, the ahci
    driver has quirks to enable or disable 64-bit DMA depending on the BIOS
    version (see ahci_sb600_enable_64bit() in ahci.c). This ahci quirk matches
    against the SB600 SATA controller, but the real issue is almost certainly
    with the RS690 PCI host that it was commonly attached to.
    
    To avoid this issue in all drivers with 64-bit DMA support, fix the
    configuration of the PCI host. If the kernel is aware of physical memory
    above 4GB, but the BIOS never configured the PCI host with this
    information, update the registers with our values.
    
    [bhelgaas: drop PCI_DEVICE_ID_ATI_RS690 definition]
    Link: https://lore.kernel.org/r/20210611214823.4898-1-mikel@xxxxxxxxxx
    Signed-off-by: Mikel Rychliski <mikel@xxxxxxxxxx>
    Signed-off-by: Bjorn Helgaas <bhelgaas@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c
index 0a0e168be1cb..9b0e771302ce 100644
--- a/arch/x86/pci/fixup.c
+++ b/arch/x86/pci/fixup.c
@@ -779,4 +779,48 @@ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1571, pci_amd_enable_64bit_bar);
 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x15b1, pci_amd_enable_64bit_bar);
 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, 0x1601, pci_amd_enable_64bit_bar);
 
+#define RS690_LOWER_TOP_OF_DRAM2	0x30
+#define RS690_LOWER_TOP_OF_DRAM2_VALID	0x1
+#define RS690_UPPER_TOP_OF_DRAM2	0x31
+#define RS690_HTIU_NB_INDEX		0xA8
+#define RS690_HTIU_NB_INDEX_WR_ENABLE	0x100
+#define RS690_HTIU_NB_DATA		0xAC
+
+/*
+ * Some BIOS implementations support RAM above 4GB, but do not configure the
+ * PCI host to respond to bus master accesses for these addresses. These
+ * implementations set the TOP_OF_DRAM_SLOT1 register correctly, so PCI DMA
+ * works as expected for addresses below 4GB.
+ *
+ * Reference: "AMD RS690 ASIC Family Register Reference Guide" (pg. 2-57)
+ * https://www.amd.com/system/files/TechDocs/43372_rs690_rrg_3.00o.pdf
+ */
+static void rs690_fix_64bit_dma(struct pci_dev *pdev)
+{
+	u32 val = 0;
+	phys_addr_t top_of_dram = __pa(high_memory - 1) + 1;
+
+	if (top_of_dram <= (1ULL << 32))
+		return;
+
+	pci_write_config_dword(pdev, RS690_HTIU_NB_INDEX,
+				RS690_LOWER_TOP_OF_DRAM2);
+	pci_read_config_dword(pdev, RS690_HTIU_NB_DATA, &val);
+
+	if (val)
+		return;
+
+	pci_info(pdev, "Adjusting top of DRAM to %pa for 64-bit DMA support\n", &top_of_dram);
+
+	pci_write_config_dword(pdev, RS690_HTIU_NB_INDEX,
+		RS690_UPPER_TOP_OF_DRAM2 | RS690_HTIU_NB_INDEX_WR_ENABLE);
+	pci_write_config_dword(pdev, RS690_HTIU_NB_DATA, top_of_dram >> 32);
+
+	pci_write_config_dword(pdev, RS690_HTIU_NB_INDEX,
+		RS690_LOWER_TOP_OF_DRAM2 | RS690_HTIU_NB_INDEX_WR_ENABLE);
+	pci_write_config_dword(pdev, RS690_HTIU_NB_DATA,
+		top_of_dram | RS690_LOWER_TOP_OF_DRAM2_VALID);
+}
+DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7910, rs690_fix_64bit_dma);
+
 #endif



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