Patch "clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callback" has been added to the 5.10-stable tree

[Sasha Levin <sashal@xxxxxxxxxx>]

This is a note to let you know that I've just added the patch titled

    clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callback

to the 5.10-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     clk-zynqmp-move-zynqmp_pll_set_mode-out-of-round_rat.patch
and it can be found in the queue-5.10 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 103af725bc7321b8ca141b8ce99da756a1163d70
Author: Quanyang Wang <quanyang.wang@xxxxxxxxxxxxx>
Date:   Tue Apr 6 23:40:15 2021 +0800

    clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callback
    
    [ Upstream commit d7fd3f9f53df8bb2212dff70f66f12cae0e1a653 ]
    
    The round_rate callback should only perform rate calculation and not
    involve calling zynqmp_pll_set_mode to change the pll mode. So let's
    move zynqmp_pll_set_mode out of round_rate and to set_rate callback.
    
    Fixes: 3fde0e16d016 ("drivers: clk: Add ZynqMP clock driver")
    Reported-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx>
    Signed-off-by: Quanyang Wang <quanyang.wang@xxxxxxxxxxxxx>
    Link: https://lore.kernel.org/r/20210406154015.602779-1-quanyang.wang@xxxxxxxxxxxxx
    Signed-off-by: Stephen Boyd <sboyd@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/clk/zynqmp/pll.c b/drivers/clk/zynqmp/pll.c
index 92f449ed38e5..03bfe62c1e62 100644
--- a/drivers/clk/zynqmp/pll.c
+++ b/drivers/clk/zynqmp/pll.c
@@ -100,9 +100,7 @@ static long zynqmp_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 	/* Enable the fractional mode if needed */
 	rate_div = (rate * FRAC_DIV) / *prate;
 	f = rate_div % FRAC_DIV;
-	zynqmp_pll_set_mode(hw, !!f);
-
-	if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) {
+	if (f) {
 		if (rate > PS_PLL_VCO_MAX) {
 			fbdiv = rate / PS_PLL_VCO_MAX;
 			rate = rate / (fbdiv + 1);
@@ -173,10 +171,12 @@ static int zynqmp_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 	long rate_div, frac, m, f;
 	int ret;
 
-	if (zynqmp_pll_get_mode(hw) == PLL_MODE_FRAC) {
-		rate_div = (rate * FRAC_DIV) / parent_rate;
+	rate_div = (rate * FRAC_DIV) / parent_rate;
+	f = rate_div % FRAC_DIV;
+	zynqmp_pll_set_mode(hw, !!f);
+
+	if (f) {
 		m = rate_div / FRAC_DIV;
-		f = rate_div % FRAC_DIV;
 		m = clamp_t(u32, m, (PLL_FBDIV_MIN), (PLL_FBDIV_MAX));
 		rate = parent_rate * m;
 		frac = (parent_rate * f) / FRAC_DIV;