Patch "drm/vc4: crtc: Reduce PV fifo threshold on hvs4" has been added to the 5.10-stable tree

[Sasha Levin <sashal@xxxxxxxxxx>]

This is a note to let you know that I've just added the patch titled

    drm/vc4: crtc: Reduce PV fifo threshold on hvs4

to the 5.10-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     drm-vc4-crtc-reduce-pv-fifo-threshold-on-hvs4.patch
and it can be found in the queue-5.10 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 24ea225895e4c2c287fee8a17daa8892975baa51
Author: Dom Cobley <popcornmix@xxxxxxxxx>
Date:   Thu Mar 18 17:13:28 2021 +0100

    drm/vc4: crtc: Reduce PV fifo threshold on hvs4
    
    [ Upstream commit eb9dfdd1ed40357b99a4201c8534c58c562e48c9 ]
    
    Experimentally have found PV on hvs4 reports fifo full
    error with expected settings and does not with one less
    
    This appears as:
    [drm:drm_atomic_helper_wait_for_flip_done] *ERROR* [CRTC:82:crtc-3] flip_done timed out
    
    with bit 10 of PV_STAT set "HVS driving pixels when the PV FIFO is full"
    
    Fixes: c8b75bca92cb ("drm/vc4: Add KMS support for Raspberry Pi.")
    Signed-off-by: Dom Cobley <popcornmix@xxxxxxxxx>
    Signed-off-by: Maxime Ripard <maxime@xxxxxxxxxx>
    Link: https://patchwork.freedesktop.org/patch/msgid/20210318161328.1471556-3-maxime@xxxxxxxxxx
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c
index 482219fb4db2..1d2416d466a3 100644
--- a/drivers/gpu/drm/vc4/vc4_crtc.c
+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
@@ -210,6 +210,7 @@ static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format)
 {
 	const struct vc4_crtc_data *crtc_data = vc4_crtc_to_vc4_crtc_data(vc4_crtc);
 	const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
+	struct vc4_dev *vc4 = to_vc4_dev(vc4_crtc->base.dev);
 	u32 fifo_len_bytes = pv_data->fifo_depth;
 
 	/*
@@ -238,6 +239,22 @@ static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format)
 		if (crtc_data->hvs_output == 5)
 			return 32;
 
+		/*
+		 * It looks like in some situations, we will overflow
+		 * the PixelValve FIFO (with the bit 10 of PV stat being
+		 * set) and stall the HVS / PV, eventually resulting in
+		 * a page flip timeout.
+		 *
+		 * Displaying the video overlay during a playback with
+		 * Kodi on an RPi3 seems to be a great solution with a
+		 * failure rate around 50%.
+		 *
+		 * Removing 1 from the FIFO full level however
+		 * seems to completely remove that issue.
+		 */
+		if (!vc4->hvs->hvs5)
+			return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX - 1;
+
 		return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX;
 	}
 }