Patch "PCI: xgene-msi: Fix race in installing chained irq handler" has been added to the 4.14-stable tree

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This is a note to let you know that I've just added the patch titled

    PCI: xgene-msi: Fix race in installing chained irq handler

to the 4.14-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     pci-xgene-msi-fix-race-in-installing-chained-irq-han.patch
and it can be found in the queue-4.14 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 47f87619f87d8d8a8ae1930b90eb3c45747b2c52
Author: Martin Kaiser <martin@xxxxxxxxx>
Date:   Fri Jan 15 22:24:35 2021 +0100

    PCI: xgene-msi: Fix race in installing chained irq handler
    
    [ Upstream commit a93c00e5f975f23592895b7e83f35de2d36b7633 ]
    
    Fix a race where a pending interrupt could be received and the handler
    called before the handler's data has been setup, by converting to
    irq_set_chained_handler_and_data().
    
    See also 2cf5a03cb29d ("PCI/keystone: Fix race in installing chained IRQ
    handler").
    
    Based on the mail discussion, it seems ok to drop the error handling.
    
    Link: https://lore.kernel.org/r/20210115212435.19940-3-martin@xxxxxxxxx
    Signed-off-by: Martin Kaiser <martin@xxxxxxxxx>
    Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@xxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/pci/host/pci-xgene-msi.c b/drivers/pci/host/pci-xgene-msi.c
index 1f42a202b021..784b3f61199e 100644
--- a/drivers/pci/host/pci-xgene-msi.c
+++ b/drivers/pci/host/pci-xgene-msi.c
@@ -393,13 +393,9 @@ static int xgene_msi_hwirq_alloc(unsigned int cpu)
 		if (!msi_group->gic_irq)
 			continue;
 
-		irq_set_chained_handler(msi_group->gic_irq,
-					xgene_msi_isr);
-		err = irq_set_handler_data(msi_group->gic_irq, msi_group);
-		if (err) {
-			pr_err("failed to register GIC IRQ handler\n");
-			return -EINVAL;
-		}
+		irq_set_chained_handler_and_data(msi_group->gic_irq,
+			xgene_msi_isr, msi_group);
+
 		/*
 		 * Statically allocate MSI GIC IRQs to each CPU core.
 		 * With 8-core X-Gene v1, 2 MSI GIC IRQs are allocated



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