This is a note to let you know that I've just added the patch titled clk: qcom: gpucc-msm8998: Add resets, cxc, fix flags on gpu_gx_gdsc to the 5.11-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: clk-qcom-gpucc-msm8998-add-resets-cxc-fix-flags-on-g.patch and it can be found in the queue-5.11 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let <stable@xxxxxxxxxxxxxxx> know about it. commit 6df490921b7650fd9b79df556aa485551a74e9b0 Author: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxxx> Date: Thu Jan 14 23:10:58 2021 +0100 clk: qcom: gpucc-msm8998: Add resets, cxc, fix flags on gpu_gx_gdsc [ Upstream commit a59c16c80bd791878cf81d1d5aae508eeb2e73f1 ] The GPU GX GDSC has GPU_GX_BCR reset and gfx3d_clk CXC, as stated on downstream kernels (and as verified upstream, because otherwise random lockups happen). Also, add PWRSTS_RET and NO_RET_PERIPH: also as found downstream, and also as verified here, to avoid GPU related lockups it is necessary to force retain mem, but *not* peripheral when enabling this GDSC (and, of course, the inverse on disablement). With this change, the GPU finally works flawlessly on my four different MSM8998 devices from two different manufacturers. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxxx> Link: https://lore.kernel.org/r/20210114221059.483390-11-angelogioacchino.delregno@xxxxxxxxxxxxxx Signed-off-by: Stephen Boyd <sboyd@xxxxxxxxxx> Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx> diff --git a/drivers/clk/qcom/gpucc-msm8998.c b/drivers/clk/qcom/gpucc-msm8998.c index 9b3923af02a1..1a518c4915b4 100644 --- a/drivers/clk/qcom/gpucc-msm8998.c +++ b/drivers/clk/qcom/gpucc-msm8998.c @@ -253,12 +253,16 @@ static struct gdsc gpu_cx_gdsc = { static struct gdsc gpu_gx_gdsc = { .gdscr = 0x1094, .clamp_io_ctrl = 0x130, + .resets = (unsigned int []){ GPU_GX_BCR }, + .reset_count = 1, + .cxcs = (unsigned int []){ 0x1098 }, + .cxc_count = 1, .pd = { .name = "gpu_gx", }, .parent = &gpu_cx_gdsc.pd, - .pwrsts = PWRSTS_OFF_ON, - .flags = CLAMP_IO | AON_RESET, + .pwrsts = PWRSTS_OFF_ON | PWRSTS_RET, + .flags = CLAMP_IO | SW_RESET | AON_RESET | NO_RET_PERIPH, }; static struct clk_regmap *gpucc_msm8998_clocks[] = {