This is a note to let you know that I've just added the patch titled drm/i915/gt: Flush before changing register state to the 5.10-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: drm-i915-gt-flush-before-changing-register-state.patch and it can be found in the queue-5.10 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let <stable@xxxxxxxxxxxxxxx> know about it. >From d5109f739c9f14a3bda249cb48b16de1065932f0 Mon Sep 17 00:00:00 2001 From: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> Date: Mon, 25 Jan 2021 22:02:47 +0000 Subject: drm/i915/gt: Flush before changing register state From: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> commit d5109f739c9f14a3bda249cb48b16de1065932f0 upstream. Flush; invalidate; change registers; invalidate; flush. Will this finally work on every device? Or will Baytrail complain again? On the positive side, we immediately see the benefit of having hsw-gt1 in CI. Fixes: ace44e13e577 ("drm/i915/gt: Clear CACHE_MODE prior to clearing residuals") Testcase: igt/gem_render_tiled_blits # hsw-gt1 Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> Cc: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx> Cc: Akeem G Abodunrin <akeem.g.abodunrin@xxxxxxxxx> Acked-by: Mika Kuoppala <mika.kuoppala@xxxxxxxxxxxxxxx> Link: https://patchwork.freedesktop.org/patch/msgid/20210125220247.31701-1-chris@xxxxxxxxxxxxxxxxxx (cherry picked from commit d30bbd62b1bfd9e0a33c3583c5a9e5d66f60cbd7) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx> Cc: Diego Calleja <diegocg@xxxxxxxxx> Cc: Hans de Goede <hdegoede@xxxxxxxxxx> Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> --- drivers/gpu/drm/i915/gt/gen7_renderclear.c | 1 + 1 file changed, 1 insertion(+) --- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c +++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c @@ -393,6 +393,7 @@ static void emit_batch(struct i915_vma * desc_count); /* Reset inherited context registers */ + gen7_emit_pipeline_flush(&cmds); gen7_emit_pipeline_invalidate(&cmds); batch_add(&cmds, MI_LOAD_REGISTER_IMM(2)); batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_0_GEN7)); Patches currently in stable-queue which might be from chris@xxxxxxxxxxxxxxxxxx are queue-5.10/drm-modes-switch-to-64bit-maths-to-avoid-integer-overflow.patch queue-5.10/drm-i915-gt-correct-surface-base-address-for-renderclear.patch queue-5.10/drm-i915-gt-flush-before-changing-register-state.patch queue-5.10/drm-i915-gt-one-more-flush-for-baytrail-clear-residuals.patch