Patch "clk: sunxi-ng: h6: Fix clock divider range on some clocks" has been added to the 5.4-stable tree

[Sasha Levin <sashal@xxxxxxxxxx>]

This is a note to let you know that I've just added the patch titled

    clk: sunxi-ng: h6: Fix clock divider range on some clocks

to the 5.4-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     clk-sunxi-ng-h6-fix-clock-divider-range-on-some-cloc.patch
and it can be found in the queue-5.4 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit a837571d58d0a8e3d5644b4d2d7570cf919e52a0
Author: Andre Przywara <andre.przywara@xxxxxxx>
Date:   Mon Jan 18 00:09:12 2021 +0000

    clk: sunxi-ng: h6: Fix clock divider range on some clocks
    
    [ Upstream commit 04ef679591c76571a9e7d5ca48316cc86fa0ef12 ]
    
    While comparing clocks between the H6 and H616, some of the M factor
    ranges were found to be wrong: the manual says they are only covering
    two bits [1:0], but our code had "5" in the number-of-bits field.
    
    By writing 0xff into that register in U-Boot and via FEL, it could be
    confirmed that bits [4:2] are indeed masked off, so the manual is right.
    
    Change to number of bits in the affected clock's description.
    
    Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
    Signed-off-by: Andre Przywara <andre.przywara@xxxxxxx>
    Reviewed-by: Jernej Skrabec <jernej.skrabec@xxxxxxxx>
    Signed-off-by: Maxime Ripard <maxime@xxxxxxxxxx>
    Link: https://lore.kernel.org/r/20210118000912.28116-1-andre.przywara@xxxxxxx
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
index 183dd350cce95..2f00f1b7b9c00 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
@@ -228,7 +228,7 @@ static const char * const psi_ahb1_ahb2_parents[] = { "osc24M", "osc32k",
 static SUNXI_CCU_MP_WITH_MUX(psi_ahb1_ahb2_clk, "psi-ahb1-ahb2",
 			     psi_ahb1_ahb2_parents,
 			     0x510,
-			     0, 5,	/* M */
+			     0, 2,	/* M */
 			     8, 2,	/* P */
 			     24, 2,	/* mux */
 			     0);
@@ -237,19 +237,19 @@ static const char * const ahb3_apb1_apb2_parents[] = { "osc24M", "osc32k",
 						       "psi-ahb1-ahb2",
 						       "pll-periph0" };
 static SUNXI_CCU_MP_WITH_MUX(ahb3_clk, "ahb3", ahb3_apb1_apb2_parents, 0x51c,
-			     0, 5,	/* M */
+			     0, 2,	/* M */
 			     8, 2,	/* P */
 			     24, 2,	/* mux */
 			     0);
 
 static SUNXI_CCU_MP_WITH_MUX(apb1_clk, "apb1", ahb3_apb1_apb2_parents, 0x520,
-			     0, 5,	/* M */
+			     0, 2,	/* M */
 			     8, 2,	/* P */
 			     24, 2,	/* mux */
 			     0);
 
 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", ahb3_apb1_apb2_parents, 0x524,
-			     0, 5,	/* M */
+			     0, 2,	/* M */
 			     8, 2,	/* P */
 			     24, 2,	/* mux */
 			     0);