Patch "irqchip/sifive-plic: Fix chip_data access within a hierarchy" has been added to the 5.9-stable tree

[Sasha Levin <sashal@xxxxxxxxxx>]

This is a note to let you know that I've just added the patch titled

    irqchip/sifive-plic: Fix chip_data access within a hierarchy

to the 5.9-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     irqchip-sifive-plic-fix-chip_data-access-within-a-hi.patch
and it can be found in the queue-5.9 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit c10f2dab0f055acbb1e163d207859a47f600f811
Author: Greentime Hu <greentime.hu@xxxxxxxxxx>
Date:   Thu Oct 29 10:37:38 2020 +0800

    irqchip/sifive-plic: Fix chip_data access within a hierarchy
    
    [ Upstream commit f9ac7bbd6e4540dcc6df621b9c9b6eb2e26ded1d ]
    
    The plic driver crashes in plic_irq_unmask() when the interrupt is within a
    hierarchy, as it picks the top-level chip_data instead of its local one.
    
    Using irq_data_get_irq_chip_data() instead of irq_get_chip_data() solves
    the issue for good.
    
    Fixes: f1ad1133b18f ("irqchip/sifive-plic: Add support for multiple PLICs")
    Signed-off-by: Greentime Hu <greentime.hu@xxxxxxxxxx>
    [maz: rewrote commit message]
    Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx>
    Reviewed-by: Anup Patel <anup@xxxxxxxxxxxxxx>
    Reviewed-by: Atish Patra <atish.patra@xxxxxxx>
    Link: https://lore.kernel.org/r/20201029023738.127472-1-greentime.hu@xxxxxxxxxx
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index 4048657ece0ac..6f432d2a5cebd 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -99,7 +99,7 @@ static inline void plic_irq_toggle(const struct cpumask *mask,
 				   struct irq_data *d, int enable)
 {
 	int cpu;
-	struct plic_priv *priv = irq_get_chip_data(d->irq);
+	struct plic_priv *priv = irq_data_get_irq_chip_data(d);
 
 	writel(enable, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID);
 	for_each_cpu(cpu, mask) {
@@ -115,7 +115,7 @@ static void plic_irq_unmask(struct irq_data *d)
 {
 	struct cpumask amask;
 	unsigned int cpu;
-	struct plic_priv *priv = irq_get_chip_data(d->irq);
+	struct plic_priv *priv = irq_data_get_irq_chip_data(d);
 
 	cpumask_and(&amask, &priv->lmask, cpu_online_mask);
 	cpu = cpumask_any_and(irq_data_get_affinity_mask(d),
@@ -127,7 +127,7 @@ static void plic_irq_unmask(struct irq_data *d)
 
 static void plic_irq_mask(struct irq_data *d)
 {
-	struct plic_priv *priv = irq_get_chip_data(d->irq);
+	struct plic_priv *priv = irq_data_get_irq_chip_data(d);
 
 	plic_irq_toggle(&priv->lmask, d, 0);
 }
@@ -138,7 +138,7 @@ static int plic_set_affinity(struct irq_data *d,
 {
 	unsigned int cpu;
 	struct cpumask amask;
-	struct plic_priv *priv = irq_get_chip_data(d->irq);
+	struct plic_priv *priv = irq_data_get_irq_chip_data(d);
 
 	cpumask_and(&amask, &priv->lmask, mask_val);