Patch "powerpc/perf: Exclude pmc5/6 from the irrelevant PMU group constraints" has been added to the 5.4-stable tree

[Sasha Levin <sashal@xxxxxxxxxx>]

This is a note to let you know that I've just added the patch titled

    powerpc/perf: Exclude pmc5/6 from the irrelevant PMU group constraints

to the 5.4-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     powerpc-perf-exclude-pmc5-6-from-the-irrelevant-pmu-.patch
and it can be found in the queue-5.4 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit a891f78d295d75a246068957d482f4660c210dbf
Author: Athira Rajeev <atrajeev@xxxxxxxxxxxxxxxxxx>
Date:   Mon Sep 21 03:10:04 2020 -0400

    powerpc/perf: Exclude pmc5/6 from the irrelevant PMU group constraints
    
    [ Upstream commit 3b6c3adbb2fa42749c3d38cfc4d4d0b7e096bb7b ]
    
    PMU counter support functions enforces event constraints for group of
    events to check if all events in a group can be monitored. Incase of
    event codes using PMC5 and PMC6 ( 500fa and 600f4 respectively ), not
    all constraints are applicable, say the threshold or sample bits. But
    current code includes pmc5 and pmc6 in some group constraints (like
    IC_DC Qualifier bits) which is actually not applicable and hence
    results in those events not getting counted when scheduled along with
    group of other events. Patch fixes this by excluding PMC5/6 from
    constraints which are not relevant for it.
    
    Fixes: 7ffd948 ("powerpc/perf: factor out power8 pmu functions")
    Signed-off-by: Athira Rajeev <atrajeev@xxxxxxxxxxxxxxxxxx>
    Reviewed-by: Madhavan Srinivasan <maddy@xxxxxxxxxxxxx>
    Signed-off-by: Michael Ellerman <mpe@xxxxxxxxxxxxxx>
    Link: https://lore.kernel.org/r/1600672204-1610-1-git-send-email-atrajeev@xxxxxxxxxxxxxxxxxx
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/arch/powerpc/perf/isa207-common.c b/arch/powerpc/perf/isa207-common.c
index 4c86da5eb28ab..0b5c8f4fbdbfd 100644
--- a/arch/powerpc/perf/isa207-common.c
+++ b/arch/powerpc/perf/isa207-common.c
@@ -269,6 +269,15 @@ int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp)
 
 		mask  |= CNST_PMC_MASK(pmc);
 		value |= CNST_PMC_VAL(pmc);
+
+		/*
+		 * PMC5 and PMC6 are used to count cycles and instructions and
+		 * they do not support most of the constraint bits. Add a check
+		 * to exclude PMC5/6 from most of the constraints except for
+		 * EBB/BHRB.
+		 */
+		if (pmc >= 5)
+			goto ebb_bhrb;
 	}
 
 	if (pmc <= 4) {
@@ -335,6 +344,7 @@ int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp)
 		}
 	}
 
+ebb_bhrb:
 	if (!pmc && ebb)
 		/* EBB events must specify the PMC */
 		return -1;