Patch "arm64: perf: Add missing ISB in armv8pmu_enable_counter()" has been added to the 5.9-stable tree

[Sasha Levin <sashal@xxxxxxxxxx>]

This is a note to let you know that I've just added the patch titled

    arm64: perf: Add missing ISB in armv8pmu_enable_counter()

to the 5.9-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     arm64-perf-add-missing-isb-in-armv8pmu_enable_counte.patch
and it can be found in the queue-5.9 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit fb027c3c400ab4ad008d9a4bbafee4d1acbedefb
Author: Alexandru Elisei <alexandru.elisei@xxxxxxx>
Date:   Thu Sep 24 12:07:00 2020 +0100

    arm64: perf: Add missing ISB in armv8pmu_enable_counter()
    
    [ Upstream commit 490d7b7c0845eacf5593db333fd2ae7715416e16 ]
    
    Writes to the PMXEVTYPER_EL0 register are not self-synchronising. In
    armv8pmu_enable_event(), the PE can reorder configuring the event type
    after we have enabled the counter and the interrupt. This can lead to an
    interrupt being asserted because of the previous event type that we were
    counting using the same counter, not the one that we've just configured.
    
    The same rationale applies to writes to the PMINTENSET_EL1 register. The PE
    can reorder enabling the interrupt at any point in the future after we have
    enabled the event.
    
    Prevent both situations from happening by adding an ISB just before we
    enable the event counter.
    
    Fixes: 030896885ade ("arm64: Performance counters support")
    Reported-by: Julien Thierry <julien.thierry@xxxxxxx>
    Signed-off-by: Alexandru Elisei <alexandru.elisei@xxxxxxx>
    Tested-by: Sumit Garg <sumit.garg@xxxxxxxxxx> (Developerbox)
    Cc: Julien Thierry <julien.thierry.kdev@xxxxxxxxx>
    Cc: Will Deacon <will.deacon@xxxxxxx>
    Cc: Mark Rutland <mark.rutland@xxxxxxx>
    Cc: Peter Zijlstra <peterz@xxxxxxxxxxxxx>
    Cc: Ingo Molnar <mingo@xxxxxxxxxx>
    Cc: Arnaldo Carvalho de Melo <acme@xxxxxxxxxx>
    Cc: Alexander Shishkin <alexander.shishkin@xxxxxxxxxxxxxxx>
    Cc: Jiri Olsa <jolsa@xxxxxxxxxx>
    Cc: Namhyung Kim <namhyung@xxxxxxxxxx>
    Cc: Catalin Marinas <catalin.marinas@xxxxxxx>
    Link: https://lore.kernel.org/r/20200924110706.254996-2-alexandru.elisei@xxxxxxx
    Signed-off-by: Will Deacon <will@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 462f9a9cc44be..481d48e3872b8 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -532,6 +532,11 @@ static u32 armv8pmu_event_cnten_mask(struct perf_event *event)
 
 static inline void armv8pmu_enable_counter(u32 mask)
 {
+	/*
+	 * Make sure event configuration register writes are visible before we
+	 * enable the counter.
+	 * */
+	isb();
 	write_sysreg(mask, pmcntenset_el0);
 }