Patch "x86/resctrl: Support CPUID enumeration of MBM counter width" has been added to the 5.7-stable tree

[Sasha Levin <sashal@xxxxxxxxxx>]

This is a note to let you know that I've just added the patch titled

    x86/resctrl: Support CPUID enumeration of MBM counter width

to the 5.7-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     x86-resctrl-support-cpuid-enumeration-of-mbm-counter.patch
and it can be found in the queue-5.7 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 974108a2ecdf65a621b5b889a3b608b334e20a01
Author: Reinette Chatre <reinette.chatre@xxxxxxxxx>
Date:   Tue May 5 15:36:17 2020 -0700

    x86/resctrl: Support CPUID enumeration of MBM counter width
    
    [ Upstream commit f3d44f18b0662327c42128b9d3604489bdb6e36f ]
    
    The original Memory Bandwidth Monitoring (MBM) architectural
    definition defines counters of up to 62 bits in the
    IA32_QM_CTR MSR while the first-generation MBM implementation
    uses statically defined 24 bit counters.
    
    Expand the MBM CPUID enumeration properties to include the MBM
    counter width. The previously undefined EAX output register contains,
    in bits [7:0], the MBM counter width encoded as an offset from
    24 bits. Enumerating this property is only specified for Intel
    CPUs.
    
    Suggested-by: Borislav Petkov <bp@xxxxxxx>
    Signed-off-by: Reinette Chatre <reinette.chatre@xxxxxxxxx>
    Signed-off-by: Borislav Petkov <bp@xxxxxxx>
    Link: https://lkml.kernel.org/r/afa3af2f753f6bc301fb743bc8944e749cb24afa.1588715690.git.reinette.chatre@xxxxxxxxx
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 3bcf27caf6c9f..c4e8fd709cf67 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -113,9 +113,10 @@ struct cpuinfo_x86 {
 	/* in KB - valid for CPUS which support this call: */
 	unsigned int		x86_cache_size;
 	int			x86_cache_alignment;	/* In bytes */
-	/* Cache QoS architectural values: */
+	/* Cache QoS architectural values, valid only on the BSP: */
 	int			x86_cache_max_rmid;	/* max index */
 	int			x86_cache_occ_scale;	/* scale to bytes */
+	int			x86_cache_mbm_width_offset;
 	int			x86_power;
 	unsigned long		loops_per_jiffy;
 	/* cpuid returned max cores value: */
diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c
index 49599733fa94d..d242e864726c0 100644
--- a/arch/x86/kernel/cpu/resctrl/core.c
+++ b/arch/x86/kernel/cpu/resctrl/core.c
@@ -963,6 +963,7 @@ void resctrl_cpu_detect(struct cpuinfo_x86 *c)
 	if (!cpu_has(c, X86_FEATURE_CQM_LLC)) {
 		c->x86_cache_max_rmid  = -1;
 		c->x86_cache_occ_scale = -1;
+		c->x86_cache_mbm_width_offset = -1;
 		return;
 	}
 
@@ -979,6 +980,10 @@ void resctrl_cpu_detect(struct cpuinfo_x86 *c)
 
 		c->x86_cache_max_rmid  = ecx;
 		c->x86_cache_occ_scale = ebx;
+		if (c->x86_vendor == X86_VENDOR_INTEL)
+			c->x86_cache_mbm_width_offset = eax & 0xff;
+		else
+			c->x86_cache_mbm_width_offset = -1;
 	}
 }