This is a note to let you know that I've just added the patch titled MIPS: BMIPS: Clear MIPS_CACHE_ALIASES earlier to the 4.4-stable tree which can be found at: http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary The filename of the patch is: mips-bmips-clear-mips_cache_aliases-earlier.patch and it can be found in the queue-4.4 subdirectory. If you, or anyone else, feels it should not be added to the stable tree, please let <stable@xxxxxxxxxxxxxxx> know about it. >From 73c4ca047f440c79f545bc6133e3033f754cd239 Mon Sep 17 00:00:00 2001 From: Florian Fainelli <f.fainelli@xxxxxxxxx> Date: Mon, 4 Apr 2016 10:55:35 -0700 Subject: MIPS: BMIPS: Clear MIPS_CACHE_ALIASES earlier From: Florian Fainelli <f.fainelli@xxxxxxxxx> commit 73c4ca047f440c79f545bc6133e3033f754cd239 upstream. BMIPS5000 and BMIPS5200 processor have no D cache aliases, and this is properly handled by the per-CPU override added at the end of r4k_cache_init(), the problem is that the output of probe_pcache() disagrees with that, since this is too late: Primary instruction cache 32kB, VIPT, 4-way, linesize 64 bytes. Primary data cache 32kB, 4-way, VIPT, cache aliases, linesize 32 bytes With the change moved earlier, we now have a consistent output with the settings we are intending to have: Primary instruction cache 32kB, VIPT, 4-way, linesize 64 bytes. Primary data cache 32kB, 4-way, VIPT, no aliases, linesize 32 bytes Fixes: d74b0172e4e2c ("MIPS: BMIPS: Add special cache handling in c-r4k.c") Signed-off-by: Florian Fainelli <f.fainelli@xxxxxxxxx> Cc: linux-mips@xxxxxxxxxxxxxx Patchwork: https://patchwork.linux-mips.org/patch/13011/ Signed-off-by: Ralf Baechle <ralf@xxxxxxxxxxxxxx> Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxxxxxxxxxxxxxx> --- arch/mips/mm/c-r4k.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1310,6 +1310,8 @@ static void probe_pcache(void) case CPU_BMIPS5000: c->icache.flags |= MIPS_CACHE_IC_F_DC; + /* Cache aliases are handled in hardware; allow HIGHMEM */ + c->dcache.flags &= ~MIPS_CACHE_ALIASES; break; case CPU_LOONGSON2: @@ -1749,8 +1751,6 @@ void r4k_cache_init(void) flush_icache_range = (void *)b5k_instruction_hazard; local_flush_icache_range = (void *)b5k_instruction_hazard; - /* Cache aliases are handled in hardware; allow HIGHMEM */ - current_cpu_data.dcache.flags &= ~MIPS_CACHE_ALIASES; /* Optimization: an L2 flush implicitly flushes the L1 */ current_cpu_data.options |= MIPS_CPU_INCLUSIVE_CACHES; Patches currently in stable-queue which might be from f.fainelli@xxxxxxxxx are queue-4.4/mips-bmips-adjust-mips-hpt-frequency-for-bcm7435.patch queue-4.4/mips-bmips-clear-mips_cache_aliases-earlier.patch queue-4.4/mips-bmips-pretty-print-bmips5200-processor-name.patch queue-4.4/mips-bmips-bmips5000-has-i-cache-filing-from-d-cache.patch queue-4.4/mips-bmips-fix-prid_imp_bmips5000-masking-for-bmips5200.patch queue-4.4/mips-smp-update-cpu_foreign_map-on-cpu-disable.patch queue-4.4/mips-bmips-local_r4k___flush_cache_all-needs-to-blast-s-cache.patch