Patch "arm64: dts: allwinner: a64: Re-add PMU node" has been added to the 5.3-stable tree

[Sasha Levin <sashal@xxxxxxxxxx>]

This is a note to let you know that I've just added the patch titled

    arm64: dts: allwinner: a64: Re-add PMU node

to the 5.3-stable tree which can be found at:
    http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
     arm64-dts-allwinner-a64-re-add-pmu-node.patch
and it can be found in the queue-5.3 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree,
please let <stable@xxxxxxxxxxxxxxx> know about it.



commit 25e5445c630c69bd7e3d05d327e15d095651b195
Author: Andre Przywara <andre.przywara@xxxxxxx>
Date:   Tue Nov 5 11:06:51 2019 +0000

    arm64: dts: allwinner: a64: Re-add PMU node
    
    [ Upstream commit 6b832a148717f1718f57805a9a4aa7f092582d15 ]
    
    As it was found recently, the Performance Monitoring Unit (PMU) on the
    Allwinner A64 SoC was not generating (the right) interrupts. With the
    SPI numbers from the manual the kernel did not receive any overflow
    interrupts, so perf was not happy at all.
    It turns out that the numbers were just off by 4, so the PMU interrupts
    are from 148 to 151, not from 152 to 155 as the manual describes.
    
    This was found by playing around with U-Boot, which typically does not
    use interrupts, so the GIC is fully available for experimentation:
    With *every* PPI and SPI enabled, an overflowing PMU cycle counter was
    found to set a bit in one of the GICD_ISPENDR registers, with careful
    counting this was determined to be number 148.
    
    Tested with perf record and perf top on a Pine64-LTS. Also tested with
    tasksetting to every core to confirm the assignment between IRQs and
    cores.
    
    This somewhat "revert-fixes" commit ed3e9406bcbc ("arm64: dts: allwinner:
    a64: Drop PMU node").
    
    Fixes: 34a97fcc71c2 ("arm64: dts: allwinner: a64: Add PMU node")
    Fixes: ed3e9406bcbc ("arm64: dts: allwinner: a64: Drop PMU node")
    Signed-off-by: Andre Przywara <andre.przywara@xxxxxxx>
    Signed-off-by: Maxime Ripard <maxime@xxxxxxxxxx>
    Signed-off-by: Sasha Levin <sashal@xxxxxxxxxx>

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index cd92f546c4838..1d362f625a405 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -142,6 +142,15 @@
 		clock-output-names = "ext-osc32k";
 	};
 
+	pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
 	psci {
 		compatible = "arm,psci-0.2";
 		method = "smc";