> 7d5ec3d36123 had the mask_all() invocation _before_ setting up the the > entries and reading back the descriptors. So that commit cannot break > the niu device when your problem analysis is correct. In 7d5ec3d36123 (and later) msix_mask_all() only writes to PCI_MSIX_ENTRY_VECTOR_CTRL. I have tried all the MSIX registers, and only writes to PCI_MSIX_ENTRY_DATA were able to prevent a fatal trap on a read. However the only write to PCI_MSIX_ENTRY_DATA I see is in __pci_write_msi_msg() for 7d5ec3d36123, or pci_write_msg_msix(), in 6.11.5. > 83dbf898a2d4 moved the mask_all() invocation after setting up MSI-X into > the success path to handle a bonkers Marvell NVME device. That then > matches your problem desription as the read proceeds the write. > > I've never heard of a similiar problem, so I'm pretty sure that's truly > niu specific. > > Thanks, > > tglx Regards, Jonathan Currier
