On Fri, May 6, 2022 at 12:20 PM Maciej W. Rozycki <macro@xxxxxxxxxxx> wrote:
> On Thu, 5 May 2022, Arnd Bergmann wrote:
> I think I'm missing something here. IIUC we're talking about a PCI/PCIe
> bus used with s390 hardware, right?
>
> (It has to be PCI/PCIe, because other than x86/IA-64 host buses there are
> only PCI/PCIe and EISA/ISA buses out there that define I/O access cycles
> and EISA/ISA have long been obsoleted except perhaps from some niche use.)
>
> If this is PCI/PCIe indeed, then an I/O access is just a different bit
> pattern put on the bus/in the TLP in the address phase. So what is there
> inherent to the s390 architecture that prevents that different bit pattern
> from being used?
The hardware design for PCI on s390 is very different from any other
architecture, and more abstract. Rather than implementing MMIO register
access as pointer dereference, this is a separate CPU instruction that
takes a device/bar plus offset as arguments rather than a pointer, and
Linux encodes this back into a fake __iomem token.
> If anything, I could imagine the same limitation as with current POWER9
> implementations, that is whatever glue is used to wire PCI/PCIe to the
> rest of the system does not implement a way to use said bit pattern (which
> has nothing to do with the POWER9 processor instruction set).
>
> But that has nothing to do with the presence or absence of any specific
> processor instructions. It's just a limitation of bus glue. So I guess
> it's just that all PCI/PCIe glue logic implementations for s390 have such
> a limitation, right?
There are separate instructions for PCI memory and config space, but
no instructions for I/O space, or for non-PCI MMIO that it could be mapped
into.
Arnd
