On Wed, Mar 31, 2021 at 02:30:37PM +0000, guoren@xxxxxxxxxx wrote: > From: Guo Ren <guoren@xxxxxxxxxxxxxxxxx> > > We don't have native hw xchg16 instruction, so let qspinlock > generic code to deal with it. > > Using the full-word atomic xchg instructions implement xchg16 has > the semantic risk for atomic operations. > > This patch cancels the dependency of on qspinlock generic code on > architecture's xchg16. > > Signed-off-by: Guo Ren <guoren@xxxxxxxxxxxxxxxxx> > Cc: Arnd Bergmann <arnd@xxxxxxxx> > Cc: Jonas Bonn <jonas@xxxxxxxxxxxx> > Cc: Stefan Kristiansson <stefan.kristiansson@xxxxxxxxxxxxx> > Cc: Stafford Horne <shorne@xxxxxxxxx> > Cc: openrisc@xxxxxxxxxxxxxxxxxxxx Acked-by: Stafford Horne <shorne@xxxxxxxxx> > --- > arch/openrisc/Kconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/openrisc/Kconfig b/arch/openrisc/Kconfig > index 591acc5990dc..b299e409429f 100644 > --- a/arch/openrisc/Kconfig > +++ b/arch/openrisc/Kconfig > @@ -33,6 +33,7 @@ config OPENRISC > select OR1K_PIC > select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1 > select ARCH_USE_QUEUED_SPINLOCKS > + select ARCH_USE_QUEUED_SPINLOCKS_XCHG32 > select ARCH_USE_QUEUED_RWLOCKS > select OMPIC if SMP > select ARCH_WANT_FRAME_POINTERS > -- > 2.17.1 >
