On Tue, 2015-10-27 at 18:54 -0700, Nishanth Aravamudan wrote: > > In "bypass" mode, what TCE size is used? Is it guaranteed to be 4K? None :-) The TCEs are completely bypassed. You get a N:M linear mapping of all memory starting at 1<<59 PCI side. > Seems like this would be a different platform implentation I'd put in > for 'powernv', is that right? > > My apologies for missing that, and thank you for the review! Cheers, Ben. -- To unsubscribe from this list: send the line "unsubscribe sparclinux" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
