From: David Ahern <david.ahern@xxxxxxxxxx> Date: Thu, 19 Mar 2015 16:06:37 -0400 > The M7 processor has a different hypervisor group id and different PCR fast > trap values. PIC read/write functions and PCR bit fields are the same as > the T4 so those are reused. > > Signed-off-by: David Ahern <david.ahern@xxxxxxxxxx> > Acked-by: Bob Picco <bob.picco@xxxxxxxxxx> Applied, but two questions: 1) Why didn't you have to deal with the overflow event latching issues I address in sparc_vt_write_pmc()? 2) How simple is it to hook up a similar set of support for sparc-m6? It seems like the only PMU type string we won't match after this. Thanks. -- To unsubscribe from this list: send the line "unsubscribe sparclinux" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
