From: David Miller <davem@xxxxxxxxxxxxx> Date: Tue, 16 Sep 2014 17:47:25 -0400 (EDT) > However I notice that 0x8 is set, which is a reserved bit. That > shouldn't happen, and could be what the hypervisor really doesn't > like. I just confirmed that this is why the hypervisor throws an error. It actually inspects all of 0xf in the PTE as a size field (rather than just 0x7) via the TTE_SIZE() macro (in include/sun4v/mmu.h), which uses TTE_SZ_MASK (also in include/sun4v/mmu.h), which is defined as 0xf. It then makes sure that only CPU supported sizes are set in the PTE by using the TTE_VALIDSIZEARRAY (f.e. in greatlakes/ontario/include/mmu.h or greatlakes/huron/include/mmu.h) bitmask, which is different for each platform hypervisor build. Anyways, we have to figure out why 0x8 is set in the PTE that we try to load into ITLB. I haven't found any smoking guns yet. -- To unsubscribe from this list: send the line "unsubscribe sparclinux" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
