Re: [PATCH v3 7/9] sparc64: Move from 4MB to 8MB huge pages.

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David Miller wrote:	[Wed Nov 13 2013, 02:18:41AM EST]
> 
> The impetus for this is that we would like to move to 64-bit PMDs and
> PGDs, but that would result in only supporting a 42-bit address space
> with the current page table layout.  It'd be nice to support at least
> 43-bits.
> 
> The reason we'd end up with only 42-bits after making PMDs and PGDs
> 64-bit is that we only use half-page sized PTE tables in order to make
> PMDs line up to 4MB, the hardware huge page size we use.
> 
> So what we do here is we make huge pages 8MB, and fabricate them using
> 4MB hw TLB entries.
> 
> Facilitate this by providing a "REAL_HPAGE_SHIFT" which is used in
> places that really need to operate on hardware 4MB pages.
> 
> Use full pages (512 entries) for PTE tables, and adjust PMD_SHIFT,
> PGD_SHIFT, and the build time CPP test as needed.  Use a CPP test to
> make sure REAL_HPAGE_SHIFT and the _PAGE_SZHUGE_* we use match up.
> 
> This makes the pgtable cache completely unused, so remove the code
> managing it and the state used in mm_context_t.  Now we have less
> spinlocks taken in the page table allocation path.
> 
> The technique we use to fabricate the 8MB pages is to transfer bit 22
> from the missing virtual address into the PTEs physical address field.
> That takes care of the transparent huge pages case.
> 
> For hugetlb, we fill things in at the PTE level and that code already
> puts the sub huge page physical bits into the PTEs, based upon the
> offset, so there is nothing special we need to do.  It all just works
> out.
> 
> So, a small amount of complexity in the THP case, but this code is
> about to get much simpler when we move the 64-bit PMDs as we can move
> away from the fancy 32-bit huge PMD encoding and just put a real PTE
> value in there.
> 
> With bug fixes and help from Bob Picco.
> 
> Signed-off-by: David S. Miller <davem@xxxxxxxxxxxxx>
> ---
Acked-by: Bob Picco <bob.picco@xxxxxxxxxx>
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