Re: sparc32: some more testing

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



Hi,

I tried to revert commit 4d14a459857bd151ecbd14bcd37b4628da00792b.
We had

UP kernel:
SS20 with SuperSPARC-II 75MHz : boots, but various binaries either
BUG, give "Illegal instruction", receive signal 4, ...
SS20 with HyperSPARC 125MHz : boots, INIT segfaults

SMP kernel:
SS20 with dual SuperSPARC-II 75MHz :  boots, loading INIT is
slooooooow ... takes like 1 minute or so ... finally system freezes
SS20 with quad HyperSPARC 125MHz : boots, INIT segfaults

Now, after reverted commit 4d14a459857bd151ecbd14bcd37b4628da00792b we have

UP dirty kernel:
SS20 with SuperSPARC-II 75MHz : boots, but various binaries either
BUG, give "Illegal instruction", receive signal 4, ...
SS20 with HyperSPARC 125MHz : works

SMP dirty kernel:
SS20 with SuperSPARC-II 75MHz : boots, but various binaries either
BUG, give "Illegal instruction", receive signal 4, ...
SS20 with quad HyperSPARC 125MHz :  boots, but system freezes shortly after INIT

M
--
To unsubscribe from this list: send the line "unsubscribe sparclinux" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at  http://vger.kernel.org/majordomo-info.html


[Index of Archives]     [Kernel Development]     [DCCP]     [Linux ARM Development]     [Linux]     [Photo]     [Yosemite Help]     [Linux ARM Kernel]     [Linux SCSI]     [Linux x86_64]     [Linux Hams]

  Powered by Linux