From: Jan Engelhardt <jengelh@xxxxxxxxxx>
Date: Fri, 21 Jan 2011 02:17:52 +0100 (CET)
> I am still a bit puzzled since the T1 is configured quite like the
> Intel i7 920:
>
> T1: 4 threads × 6 cores × 1 CPU
> core_sibling_list=0-3, thread_sibling_list=0-3
>
> i7: 2 threads × 4 cores × 1 CPU
> core_sibling_list=0-7, thread_sibling_list=0,4
>
> And in comparison:
> Altix4700: 2 threads × 2 cores × 128 CPUs
> cpu0/core_sibling=0x03 (inferring>) core_sibling_list=0-3
> cpu0/thread_sibling=0x01 (inferring>) thread_sibling_list=0-1
>
>
> So it seems as if, because the toplogy is different between sparc
> and {ia64, x86}, at least one has worse scheduling.
This is to make room for T2's design, wherein inside of a core there
are two integer units.
So in the T2 we get:
cpu0 --> cpu7 --> core_id == 1
cpu8 --> cpu15 --> core_id == 2
cpu0 --> cpu3 --> phys_package_id == 0
cpu4 --> cpu7 --> phys_package_id == 1
cpu8 --> cpu11 --> phys_package_id == 2
cpu12 --> cpu15 --> phys_package_id == 3
etc. etc. etc.
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