memory barriers on sparc

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



Someone asked a question on comp.programming.threads about memory
barriers, which led me to the discovery that glibc and the kernel use
different semantics for memory barriers on sparc64 (and maybe sparc too,
didn't check).

The kernel uses:

read : LoadLoad
write : StoreStore

This matches my understanding of the behaviour of other architectures as
well.  I got confused when I saw that glibc (as of 2.8 at least) uses:

read: LoadLoad | LoadStore
write: StoreLoad | StoreStore

I'm curious about the difference.  Could someone explain why glibc uses
additional restrictions and the kernel doesn't?

Thanks,

Chris

--
To unsubscribe from this list: send the line "unsubscribe sparclinux" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at  http://vger.kernel.org/majordomo-info.html

[Index of Archives]     [Kernel Development]     [DCCP]     [Linux ARM Development]     [Linux]     [Photo]     [Yosemite Help]     [Linux ARM Kernel]     [Linux SCSI]     [Linux x86_64]     [Linux Hams]

  Powered by Linux