From: Alan Stern <stern@xxxxxxxxxxxxxxxxxxx> Date: Thu, 21 Aug 2008 12:40:01 -0400 (EDT) > On Thu, 21 Aug 2008, Meelis Roos wrote: > > > > The earlier ohci_writel call is supposed to clear the RHSC > > > interrupt-status bit. You can test whether that worked by printing out > > > > > > ohci_readl(ohci, ®s->intrstatus) & OHCI_INTR_RHSC > > > > returns 64 always (seems to be OHCI_INTR_RHSC). > > Possibly indicating that the interrupt is level-triggered rather than > edge-triggered. Before the OHCI_INTR_RHSC disabling code was moved to the main OHCI interrupt handler, it was happening after the root hub status was read. Perhaps that was important to clear the interrupt reliably? Just for documentation, when an interrupt handler returns on sparc64 we hit the interrupt clear register for that interrupt source. This causes the state machine in the PCI controller (or wherever) to resample the interrupt signal coming from the device. If the device is still showing an interrupt, we'll get another interrupt packet and go through this sequence again. -- To unsubscribe from this list: send the line "unsubscribe sparclinux" in the body of a message to majordomo@xxxxxxxxxxxxxxx More majordomo info at http://vger.kernel.org/majordomo-info.html
