Re: [sparc64] Strange interaction between 2.6 kernel and 2.5 (and 2.6) glibc

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On Mon, Jul 30, 2007 at 09:04:27AM +0200, BERTRAND Joël <joel.bertrand@xxxxxxxxxxx> wrote:
[snip]
>> You seem to see the problem only on the systems that have the 450Mhz
>> cpus, any chance you can test the ultra60 with a different cpu
>> variant?  Perhaps those chips are part of the problem.
>
> 	And we can explain why on my U2/SMP (Uii@296MHz), I cannot reproduce the 
> bug. I only have Uii@296 MHz and Uii@450 MHz, and I cannot switch CPU's 
> between my U2 and one of my U60 (I need a running U2). If you want, I can 
> open a ssh access on one of my U60 to do some tests.
> What's cache size on your CPU's ? 450 has 4 MB, 296, only 2 MB.
>
> 	Gavin, what are your CPU's ?

My Sun box is a Sun Ultra 5 with just one processor: a TI UltraSparc IIi 
(Sabre). From memory, it is 333MHz with 2MB cache.

gavin,


[Please cc: me as I'm not on this list. Thanks.]
-- 
Wonder is the beginning of all science.
	-- Aristotle

Gavin Duley
<gduley@xxxxxxxxxx>   <gduley@xxxxxxxxxxxxxxxxx>
http://www-personal.une.edu.au/~gduley/
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