Dnia 26-08-2006 o godz. 1:24 David Miller napisał(a):
> This new fallback is "36 * 1024", ie. 36K? That doesn't make any
> sense. I thought the smallest SM40 cache size was 512K or
something
> like that.
>
According to the documentation I found ("Supersparc II Addendum"
by Sun), the Supersparc processors have 20KB instruction cache
and 16 KB data cache on CPU. The SMX0 modules were modules
without the L2 cache so only cache on CPU is counted.
That max_cache_size counting procedure counts only L2 cache as it
is much bigger than L1. Thus for SMX0 modules it may give 0 (I
have no such SMP machine to test). At least one SMP configuration
was sold with such CPUs - it was called SparcStation 10/402 (it
can be found mentioned on specrate listings).
I peeked into the i386 code and found that for original Pentium
the max_cache_size is set to 16KB. The Pentium has 8KB
instruction cache and 8KB data cache (both L1 as it has no L2 on
he CPU). So I did the same for the Supersparcs.
> If anything it should be a power of two, not some weird number
> like 36K.
I added 20KB and 16Kb and got 36KB total cache size.
Regards,
Krzysztof
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