On Mon, Feb 10, 2025 at 7:36 PM Valentin Schneider <vschneid@xxxxxxxxxx> wrote: > What if isolated CPUs unconditionally did a TLBi as late as possible in > the stack right before returning to userspace? This would mean that upon > re-entering the kernel, an isolated CPU's TLB wouldn't contain any kernel > range translation - with the exception of whatever lies between the > last-minute flush and the actual userspace entry, which should be feasible > to vet? Then AFAICT there wouldn't be any work/flush to defer, the IPI > could be entirely silenced if it targets an isolated CPU. Two issues with that: 1. I think the "Common not Private" feature Will Deacon referred to is incompatible with this idea: <https://developer.arm.com/documentation/101811/0104/Address-spaces/Common-not-Private> says "When the CnP bit is set, the software promises to use the ASIDs and VMIDs in the same way on all processors, which allows the TLB entries that are created by one processor to be used by another" 2. It's wrong to assume that TLB entries are only populated for addresses you access - thanks to speculative execution, you have to assume that the CPU might be populating random TLB entries all over the place.
