On Wed, Mar 13, 2024 at 08:09:28AM -0700, Sean Christopherson wrote: > On Wed, Mar 13, 2024, Yan Zhao wrote: > > > We'll certain fix the security hole on CPUs w/ self-snoop. In this case > > > CPU accesses are guaranteed to be coherent and the vulnerability can > > > only be exposed via non-coherent DMA which is supposed to be fixed > > > by your coming series. > > > > > > But for old CPUs w/o self-snoop the hole can be exploited using either CPU > > > or non-coherent DMA once the guest PAT is honored. As long as nobody > > > is willing to actually fix the CPU path (is it possible?) I'm kind of convinced > > We can cook a patch to check CPU self-snoop and force WB in EPT even for > > non-coherent DMA if no self-snoop. Then back porting such a patch together > > with the IOMMU side mitigation for non-coherent DMA. > > Please don't. This is a "let sleeping dogs lie" situation. > > let sleeping dogs lie - avoid interfering in a situation that is currently > causing no problems but might do so as a result of such interference. > > Yes, there is technically a flaw, but we have zero evidence that anyone cares or > that it is actually problematic in practice. On the other hand, any functional > change we make has a non-zero changes of breaking existing setups that have worked > for many years. > > > Otherwise, IOMMU side mitigation alone is meaningless for platforms of CPU of > > no self-snoop. > > > > > by Sean that sustaining the old behavior is probably the best option... > > Yes, as long as we think exposing secuirty hole on those platforms is acceptable. > > Yes, I think it's acceptable. Obviously not ideal, but given the alternatives, > I think it is a reasonable risk. > > Being 100% secure is simply not possible. Security is often about balancing the > risk/threat against the cost. In this case, the risk is low (old hardware, > uncommon setup for untrusted guests, small window of opportunity, and limited > data exposure), whereas the cost is high (decent chance of breaking existing VMs). Ok, thanks for explanation! I still have one last question: if in future there are CPUs with no selfsnoop (for some unknown reason, or just paranoid), do we allow this unsafe honoring of guest memory type for non-coherent DMAs?
