Re: [PATCH v9 0/8] Parallel CPU bringup for x86_64

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On Tue, 2023-02-21 at 09:44 +0100, Oleksandr Natalenko wrote:
> On 21.02.2023 09:35, David Woodhouse wrote:
> > On Tue, 2023-02-21 at 09:25 +0100, Oleksandr Natalenko wrote:
> > > 
> > > 
> > > Right, sorry. Here it is: http://ix.io/4oLq
> > 
> > $ echo `grep ^00000001 4oLq  | cut -c36-37`
> > 00 02 04 06 08 0a 0c 0e 10 12 14 16 18 1a 1c 1e 01 03 05 07 09 0b 0d 0f
> > 11 13 15 17 19 1b 1d 1f
> > 
> > Well they look sane enough. All even APIC IDs and then all the odd ones
> > is a topology that isn't massively surprising.
> > 
> > Does it match what you get *before* suspend/resume?
> 
> Yes, the output is completely the same after a fresh boot and after a
> suspend/resume cycle.
> 
> > Obviously we could stick our fingers in our ears and go "la la la" and
> > just disable it for non-X2APIC, for AMD without X2APIC, or perhaps
> > disable it on *resume* but still use it at boot. But I'd really like to
> > understand what's going on and not do voodoo. Thanks for helping!
> 

Hm...

Why does arch/x86/kernel/acpi/sleep.c::x86_acpi_suspend_lowlevel() set 

    initial_gs = per_cpu_offset(smp_processor_id()) ? 

Would it not be CPU#0 that comes back up, and should it not get
per_cpu_offset(0) ? 

Or maybe we should just set up smpboot_control for the CPU to find its
own stuff, *even* on waking. Since the structures are already set up,
it isn't like a clean boot.

If you let it boot in parallel mode, what if you just *remove* the line
that sets smpboot_control=0 ? 

Attachment: smime.p7s
Description: S/MIME cryptographic signature


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