On Fri, Dec 03, 2021 at 07:48:08PM -0800, Randy Dunlap wrote: > On 12/1/21 12:35, Thomas Gleixner wrote: > > +Aside of that many architectures have to save register state, e.g. debug or > > state (e.g. debug) or > > > +cause registers before another exception of the same type can happen. A > > ^^^^^ cannot parse (with or without the change to the previous line) I think the difficulty here is with "cause register"? That' a register which indicates the cause of an exception, e.g. * MIPS has `cause` (coprocessor 0 register 13) * arm64 / AArch64 has `ESR_ELx` (Exception Syndrome Register, ELx) We could probably clarify this as "exception cause registers" or "exception status registers", if that helps? Thanks, Mark.
