On Mon, 23 Dec 2024 at 09:35, Conor Dooley <conor@xxxxxxxxxx> wrote:
>
> On Mon, Dec 23, 2024 at 09:16:38AM +0800, Chunyan Zhang wrote:
> > Hi Conor,
> >
> > On Sat, 21 Dec 2024 at 06:52, Conor Dooley <conor@xxxxxxxxxx> wrote:
> > >
> > > On Fri, Dec 20, 2024 at 07:40:23PM +0800, Chunyan Zhang wrote:
> > > > The assembly is originally based on the ARM NEON and int.uc, but uses
> > > > RISC-V vector instructions to implement the RAID6 syndrome and
> > > > recovery calculations.
> > > >
> > > > The functions are tested on QEMU.
> > > >
> > > > Signed-off-by: Chunyan Zhang <zhangchunyan@xxxxxxxxxxx>
> > > > ---
> > > > include/linux/raid/pq.h | 4 +
> > > > lib/raid6/Makefile | 3 +
> > > > lib/raid6/algos.c | 8 +
> > > > lib/raid6/recov_rvv.c | 229 +++++++++++++
> > > > lib/raid6/rvv.c | 715 ++++++++++++++++++++++++++++++++++++++++
> > > > 5 files changed, 959 insertions(+)
> > > > create mode 100644 lib/raid6/recov_rvv.c
> > > > create mode 100644 lib/raid6/rvv.c
> > > >
> > > > diff --git a/include/linux/raid/pq.h b/include/linux/raid/pq.h
> > > > index 98030accf641..4c21f06c662a 100644
> > > > --- a/include/linux/raid/pq.h
> > > > +++ b/include/linux/raid/pq.h
> > > > @@ -108,6 +108,9 @@ extern const struct raid6_calls raid6_vpermxor4;
> > > > extern const struct raid6_calls raid6_vpermxor8;
> > > > extern const struct raid6_calls raid6_lsx;
> > > > extern const struct raid6_calls raid6_lasx;
> > > > +extern const struct raid6_calls raid6_rvvx1;
> > > > +extern const struct raid6_calls raid6_rvvx2;
> > > > +extern const struct raid6_calls raid6_rvvx4;
> > > >
> > > > struct raid6_recov_calls {
> > > > void (*data2)(int, size_t, int, int, void **);
> > > > @@ -125,6 +128,7 @@ extern const struct raid6_recov_calls raid6_recov_s390xc;
> > > > extern const struct raid6_recov_calls raid6_recov_neon;
> > > > extern const struct raid6_recov_calls raid6_recov_lsx;
> > > > extern const struct raid6_recov_calls raid6_recov_lasx;
> > > > +extern const struct raid6_recov_calls raid6_recov_rvv;
> > > >
> > > > extern const struct raid6_calls raid6_neonx1;
> > > > extern const struct raid6_calls raid6_neonx2;
> > > > diff --git a/lib/raid6/Makefile b/lib/raid6/Makefile
> > > > index 29127dd05d63..e62fb7cd773e 100644
> > > > --- a/lib/raid6/Makefile
> > > > +++ b/lib/raid6/Makefile
> > > > @@ -10,6 +10,9 @@ raid6_pq-$(CONFIG_ALTIVEC) += altivec1.o altivec2.o altivec4.o altivec8.o \
> > > > raid6_pq-$(CONFIG_KERNEL_MODE_NEON) += neon.o neon1.o neon2.o neon4.o neon8.o recov_neon.o recov_neon_inner.o
> > > > raid6_pq-$(CONFIG_S390) += s390vx8.o recov_s390xc.o
> > > > raid6_pq-$(CONFIG_LOONGARCH) += loongarch_simd.o recov_loongarch_simd.o
> > > > +raid6_pq-$(CONFIG_RISCV_ISA_V) += rvv.o recov_rvv.o
> > > > +CFLAGS_rvv.o += -march=rv64gcv
> > > > +CFLAGS_recov_rvv.o += -march=rv64gcv
> > >
> > > I'm curious - why do you need this when you're using .option arch,+v
> > > below?
> >
> > Compiler would complain the errors like below without this flag:
> >
> > Error: unrecognized opcode `vle8.v v0,(a3)', extension `v' or `zve64x'
> > or `zve32x' required
>
> Right, but the reason for using .option arch,+v elsewhere in the kernel
> is because we don't want the compiler to generate vector code at all,
> and the directive lets the assembler handle the vector instructions. If
> I recall correctly, the error you pasted above is from the assembler,
Yes, it is from the assembler.
> not the compiler. You should be able to just set AFLAGS, given that all
It complains the same errors after simply replacing CFLAGS with AFLAGS
here. What am I missing?
Thanks,
Chunyan
> of the vector code you're adding is hand written as far as I can see.
>
> > > > hostprogs += mktables
> > > >
> > > > diff --git a/lib/raid6/algos.c b/lib/raid6/algos.c
> > > > index cd2e88ee1f14..0a388a605131 100644
> > > > --- a/lib/raid6/algos.c
> > > > +++ b/lib/raid6/algos.c
> > > > @@ -80,6 +80,11 @@ const struct raid6_calls * const raid6_algos[] = {
> > > > #ifdef CONFIG_CPU_HAS_LSX
> > > > &raid6_lsx,
> > > > #endif
> > > > +#endif
> > > > +#ifdef CONFIG_RISCV_ISA_V
> > > > + &raid6_rvvx1,
> > > > + &raid6_rvvx2,
> > > > + &raid6_rvvx4,
> > > > #endif
> > > > &raid6_intx8,
> > > > &raid6_intx4,
> > > > @@ -115,6 +120,9 @@ const struct raid6_recov_calls *const raid6_recov_algos[] = {
> > > > #ifdef CONFIG_CPU_HAS_LSX
> > > > &raid6_recov_lsx,
> > > > #endif
> > > > +#endif
> > > > +#ifdef CONFIG_RISCV_ISA_V
> > > > + &raid6_recov_rvv,
> > > > #endif
> > > > &raid6_recov_intx1,
> > > > NULL
> > > > diff --git a/lib/raid6/recov_rvv.c b/lib/raid6/recov_rvv.c
> > > > new file mode 100644
> > > > index 000000000000..8ae74803ea7f
> > > > --- /dev/null
> > > > +++ b/lib/raid6/recov_rvv.c
> > > > @@ -0,0 +1,229 @@
> > > > +// SPDX-License-Identifier: GPL-2.0-only
> > > > +/*
> > > > + * Copyright 2024 Institute of Software, CAS.
> > > > + * Author: Chunyan Zhang <zhangchunyan@xxxxxxxxxxx>
> > > > + */
> > > > +
> > > > +#include <asm/simd.h>
> > > > +#include <asm/vector.h>
> > > > +#include <crypto/internal/simd.h>
> > > > +#include <linux/raid/pq.h>
> > > > +
> > > > +static void __raid6_2data_recov_rvv(int bytes, u8 *p, u8 *q, u8 *dp,
> > > > + u8 *dq, const u8 *pbmul,
> > > > + const u8 *qmul)
> > > > +{
> > > > + asm volatile (
> > > > + ".option push\n"
> > > > + ".option arch,+v\n"
