On Sat, 16 Nov 2024 16:45:46 +0100, Hans de Goede wrote:
> Gemini Lake (Goldmont Plus) is an Apollo Lake (Goldmont) derived design and
> as such has the P2SB at device.function 13.0, rather then at the default
> 31.1, just like Apollo Lake.
>
> At a mapping to P2SB_DEVFN_GOLDMONT to p2sb_cpu_ids[] for Goldmont Plus,
> so that the correct PCI bar gets cached.
>
> [...]
Thank you for your contribution, it has been applied to my local
review-ilpo branch. Note it will show up in the public
platform-drivers-x86/review-ilpo branch only once I've pushed my
local branch there, which might take a while.
The list of commits applied:
[1/1] platform/x86: p2sb: Cache correct PCI bar for P2SB on Gemini Lake
commit: c6a2b4fcec5f2d80b0183fae1117f06127584c28
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i.
