Re: [PATCH] platform/x86: p2sb: Cache correct PCI bar for P2SB on Denverton and Gemini Lake

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On Thu, Nov 14, 2024 at 9:36 PM Hans de Goede <hdegoede@xxxxxxxxxx> wrote:
>
> Gemine Lake (Goldmont Plus) is an Apollo Lake (Goldmont) derived design and

Gemini

> as such has the P2SB at device.function 13.0, rather then at the default
> 31.1, just like Apollo Lake.
>
> At a mapping to P2SB_DEVFN_GOLDMONT to p2sb_cpu_ids[] for Goldmont Plus,
> so that the correct PCI bar gets cached.
>
> This fixes P2SB unhiding not working on these devices, which fixes
> SPI support for the bootrom SPI controller not working.

Reviewed-by: Andy Shevchenko <andy@xxxxxxxxxx>

--
With Best Regards,
Andy Shevchenko





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