On 10/22/2024 6:52 PM, Ilpo Järvinen wrote:
On Tue, 22 Oct 2024, Mario Limonciello wrote:
On 10/22/2024 00:54, Basavaraj Natikar wrote:
On 10/22/2024 2:05 AM, Armin Wolf wrote:
Am 21.10.24 um 18:58 schrieb Basavaraj Natikar:
AMD X3D processors, also known as AMD 3D V-Cache, feature dual Core
Complex Dies (CCDs) and enlarged L3 cache, enabling dynamic mode
switching between Frequency and Cache modes. To optimize performance,
implement the AMD 3D V-Cache Optimizer, which allows selecting either:
Frequency mode: cores within the faster CCD are prioritized before
those in the slower CCD.
Cache mode: cores within the larger L3 CCD are prioritized before
those in the smaller L3 CCD.
Co-developed-by: Perry Yuan <perry.yuan@xxxxxxx>
Signed-off-by: Perry Yuan <perry.yuan@xxxxxxx>
Co-developed-by: Mario Limonciello <mario.limonciello@xxxxxxx>
Signed-off-by: Mario Limonciello <mario.limonciello@xxxxxxx>
Reviewed-by: Shyam Sundar S K <Shyam-sundar.S-k@xxxxxxx>
Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@xxxxxxx>
+static int amd_x3d_resume_handler(struct device *dev)
+{
+ struct amd_x3d_dev *data = dev_get_drvdata(dev);
+ int ret = amd_x3d_get_mode(data);
+
+ ret = amd_x3d_mode_switch(data, ret);
+ if (ret < 0)
+ return ret;
+
+ return 0;
Please directly return the result of amd_x3d_mode_switch() here.
Also i think that maybe there exists a way to avoid locking data->lock
twice
during resume, but i will leave that to you.
I will leave as it is.
Other than that:
Reviewed-by: Armin Wolf <W_Armin@xxxxxx>
Thanks for the feedback. I will re-spin a new version after looking for more
feedback from others. Thanks, -- Basavaraj
FYI - if no other feedback comes in there is no need to re-spin just to add
R-b tags. Maintainers will automatically pick them up when they use 'b4
$LORE_URL'.
?? There's the return change requested above.
Yes, I will include above return change and re-spin a new version after
looking for more feedback from others.
Thanks,
--
Basavaraj
