On Thu, 25 May 2023, Shyam Sundar S K wrote:
> Starting from Pink Sardine, number of IP blocks were added to the SoC
> and the PMFW has the ability to give debug stats on each the IP blocks
> after a S0ix cycle within part of the SMU metrics table.
>
> To differentiate this change, the 's2d_msg_id' is also changed.
This sounds a bit vague. I'd have simply said:
Pink Sardine also has different s2d message id.
...but consider replacing "s2d message id" with "Spill to DRAM message
port offset" if that's correct way to say things. I picked up that
wording from the comment in one of the contexts below, perhaps that
comment should no longer be there as the relevant define now got removed?
> Add these new capabilities to the driver.
>
> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@xxxxxxx>
The code change itself looks fine.
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@xxxxxxxxxxxxxxx>
> ---
> drivers/platform/x86/amd/pmc.c | 53 ++++++++++++++++++++++++++--------
> 1 file changed, 41 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/platform/x86/amd/pmc.c b/drivers/platform/x86/amd/pmc.c
> index c2f03cdc9ca9..f7bda8a64c95 100644
> --- a/drivers/platform/x86/amd/pmc.c
> +++ b/drivers/platform/x86/amd/pmc.c
> @@ -45,7 +45,6 @@
> #define AMD_PMC_STB_DUMMY_PC 0xC6000007
>
> /* STB S2D(Spill to DRAM) has different message port offset */
> -#define STB_SPILL_TO_DRAM 0xBE
> #define AMD_S2D_REGISTER_MESSAGE 0xA20
> #define AMD_S2D_REGISTER_RESPONSE 0xA80
> #define AMD_S2D_REGISTER_ARGUMENT 0xA88
> @@ -99,7 +98,6 @@
> #define PMC_MSG_DELAY_MIN_US 50
> #define RESPONSE_REGISTER_LOOP_MAX 20000
>
> -#define SOC_SUBSYSTEM_IP_MAX 12
> #define DELAY_MIN_US 2000
> #define DELAY_MAX_US 3000
> #define FIFO_SIZE 4096
> @@ -133,9 +131,18 @@ static const struct amd_pmc_bit_map soc15_ip_blk[] = {
> {"ISP", BIT(6)},
> {"NBIO", BIT(7)},
> {"DF", BIT(8)},
> - {"USB0", BIT(9)},
> - {"USB1", BIT(10)},
> + {"USB3_0", BIT(9)},
> + {"USB3_1", BIT(10)},
> {"LAPIC", BIT(11)},
> + {"USB3_2", BIT(12)},
> + {"USB3_3", BIT(13)},
> + {"USB3_4", BIT(14)},
> + {"USB4_0", BIT(15)},
> + {"USB4_1", BIT(16)},
> + {"MPM", BIT(17)},
> + {"JPEG", BIT(18)},
> + {"IPU", BIT(19)},
> + {"UMSCH", BIT(20)},
> {}
> };
>
> @@ -149,6 +156,8 @@ struct amd_pmc_dev {
> u32 cpu_id;
> u32 active_ips;
> u32 dram_size;
> + u32 num_ips;
> + u32 s2d_msg_id;
> /* SMU version information */
> u8 smu_program;
> u8 major;
> @@ -196,8 +205,8 @@ struct smu_metrics {
> u64 timein_s0i3_totaltime;
> u64 timein_swdrips_lastcapture;
> u64 timein_swdrips_totaltime;
> - u64 timecondition_notmet_lastcapture[SOC_SUBSYSTEM_IP_MAX];
> - u64 timecondition_notmet_totaltime[SOC_SUBSYSTEM_IP_MAX];
> + u64 timecondition_notmet_lastcapture[32];
> + u64 timecondition_notmet_totaltime[32];
> } __packed;
>
> static int amd_pmc_stb_debugfs_open(struct inode *inode, struct file *filp)
> @@ -263,7 +272,7 @@ static int amd_pmc_stb_debugfs_open_v2(struct inode *inode, struct file *filp)
> dev->msg_port = 1;
>
> /* Get the num_samples to calculate the last push location */
> - ret = amd_pmc_send_cmd(dev, S2D_NUM_SAMPLES, &num_samples, STB_SPILL_TO_DRAM, true);
> + ret = amd_pmc_send_cmd(dev, S2D_NUM_SAMPLES, &num_samples, dev->s2d_msg_id, true);
> /* Clear msg_port for other SMU operation */
> dev->msg_port = 0;
> if (ret) {
> @@ -310,6 +319,23 @@ static const struct file_operations amd_pmc_stb_debugfs_fops_v2 = {
> .release = amd_pmc_stb_debugfs_release_v2,
> };
>
> +static void amd_pmc_get_ip_info(struct amd_pmc_dev *dev)
> +{
> + switch (dev->cpu_id) {
> + case AMD_CPU_ID_PCO:
> + case AMD_CPU_ID_RN:
> + case AMD_CPU_ID_YC:
> + case AMD_CPU_ID_CB:
> + dev->num_ips = 12;
> + dev->s2d_msg_id = 0xBE;
> + break;
> + case AMD_CPU_ID_PS:
> + dev->num_ips = 21;
> + dev->s2d_msg_id = 0x85;
> + break;
> + }
> +}
> +
> static int amd_pmc_setup_smu_logging(struct amd_pmc_dev *dev)
> {
> if (dev->cpu_id == AMD_CPU_ID_PCO) {
> @@ -471,7 +497,7 @@ static int smu_fw_info_show(struct seq_file *s, void *unused)
> table.timeto_resume_to_os_lastcapture);
>
> seq_puts(s, "\n=== Active time (in us) ===\n");
> - for (idx = 0 ; idx < SOC_SUBSYSTEM_IP_MAX ; idx++) {
> + for (idx = 0 ; idx < dev->num_ips ; idx++) {
> if (soc15_ip_blk[idx].bit_mask & dev->active_ips)
> seq_printf(s, "%-8s : %lld\n", soc15_ip_blk[idx].name,
> table.timecondition_notmet_lastcapture[idx]);
> @@ -919,7 +945,7 @@ static int amd_pmc_get_dram_size(struct amd_pmc_dev *dev)
> goto err_dram_size;
> }
>
> - ret = amd_pmc_send_cmd(dev, S2D_DRAM_SIZE, &dev->dram_size, STB_SPILL_TO_DRAM, true);
> + ret = amd_pmc_send_cmd(dev, S2D_DRAM_SIZE, &dev->dram_size, dev->s2d_msg_id, true);
> if (ret || !dev->dram_size)
> goto err_dram_size;
>
> @@ -940,7 +966,10 @@ static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
> /* Spill to DRAM feature uses separate SMU message port */
> dev->msg_port = 1;
>
> - amd_pmc_send_cmd(dev, S2D_TELEMETRY_SIZE, &size, STB_SPILL_TO_DRAM, true);
> + /* Get num of IP blocks within the SoC */
> + amd_pmc_get_ip_info(dev);
> +
> + amd_pmc_send_cmd(dev, S2D_TELEMETRY_SIZE, &size, dev->s2d_msg_id, true);
> if (size != S2D_TELEMETRY_BYTES_MAX)
> return -EIO;
>
> @@ -950,8 +979,8 @@ static int amd_pmc_s2d_init(struct amd_pmc_dev *dev)
> dev->dram_size = S2D_TELEMETRY_DRAMBYTES_MAX;
>
> /* Get STB DRAM address */
> - amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_LOW, &phys_addr_low, STB_SPILL_TO_DRAM, true);
> - amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_HIGH, &phys_addr_hi, STB_SPILL_TO_DRAM, true);
> + amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_LOW, &phys_addr_low, dev->s2d_msg_id, true);
> + amd_pmc_send_cmd(dev, S2D_PHYS_ADDR_HIGH, &phys_addr_hi, dev->s2d_msg_id, true);
>
> stb_phys_addr = ((u64)phys_addr_hi << 32 | phys_addr_low);
>
>
--
i.
