Re: [PATCH 1/1] amd-pmu: fix s2idle failures on certain AMD laptops

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Hi,

On 11/30/21 05:15, Fabrizio Bertocci wrote:
> On some AMD hardware laptops, the system fails communicating with the
> PMU when entering s2idle and the machine is battery powered.
> 
> Hardware description: HP Pavilion Aero Laptop 13-be0097nr
> CPU: AMD Ryzen 7 5800U with Radeon Graphics
> GPU: 03:00.0 VGA compatible controller [0300]: Advanced Micro Devices,
> Inc. [AMD/ATI] Device [1002:1638] (rev c1)
> 
> Detailed description of the problem (and investigation) here:
> https://gitlab.freedesktop.org/drm/amd/-/issues/1799
> 
> Patch is a single line: reduce the polling delay in half, from 100uSec
> to 50uSec when waiting for a change in state from the PMC after a
> write command operation.
> 
> Tested on kernel tree detached at tag 5.14
> (7d2a07b769330c34b4deabeed939325c77a7ec2f)
> After changing the delay, I did not see a single failure on this
> machine (I have this fix for now more than one week and s2idle worked
> every single time on battery power).
> 
> Signed-off-by: Fabrizio Bertocci <fabriziobertocci@xxxxxxxxx>

Thank you for your patch, I've applied this patch to my review-hans 
branch:
https://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86.git/log/?h=review-hans

Note it will show up in my review-hans branch once I've pushed my
local branch there, which might take a while.

Once I've run some tests on this branch the patches there will be
added to the platform-drivers-x86/for-next branch and eventually
will be included in the pdx86 pull-request to Linus for the next
merge-window.

Regards,

Hans

> ---
> diff --git a/drivers/platform/x86/amd-pmc.c b/drivers/platform/x86/amd-pmc.c
> index b7e50ed050a8..841c44cd64c2 100644
> --- a/drivers/platform/x86/amd-pmc.c
> +++ b/drivers/platform/x86/amd-pmc.c
> @@ -76,7 +76,7 @@
>  #define AMD_CPU_ID_CZN                 AMD_CPU_ID_RN
>  #define AMD_CPU_ID_YC                  0x14B5
> 
> -#define PMC_MSG_DELAY_MIN_US           100
> +#define PMC_MSG_DELAY_MIN_US           50
>  #define RESPONSE_REGISTER_LOOP_MAX     20000
> 
>  #define SOC_SUBSYSTEM_IP_MAX   12
> ---
> 




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