Hi,
On 9/27/21 1:10 PM, Mauro Carvalho Chehab wrote:
> The ReST format requires blank lines before/after identation changes,
> for it to properly detect lists.
>
> Fixes: ee7abc105e2b ("platform/x86: intel_pmc_core: export platform global reset bits via etr3 sysfs file")
> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@xxxxxxxxxx>
Thank you for your patch, I've applied this patch to my review-hans
branch:
https://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86.git/log/?h=review-hans
Note it will show up in my review-hans branch once I've pushed my
local branch there, which might take a while.
Once I've run some tests on this branch the patches there will be
added to the platform-drivers-x86/for-next branch and eventually
will be included in the pdx86 pull-request to Linus for the next
merge-window.
Regards,
Hans
> ---
>
> See [PATCH 0/7] at: https://lore.kernel.org/all/cover.1632740376.git.mchehab+huawei@xxxxxxxxxx/T/#t
>
> Documentation/ABI/testing/sysfs-platform-intel-pmc | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/ABI/testing/sysfs-platform-intel-pmc b/Documentation/ABI/testing/sysfs-platform-intel-pmc
> index ef199af75ab0..f31d59b21f9b 100644
> --- a/Documentation/ABI/testing/sysfs-platform-intel-pmc
> +++ b/Documentation/ABI/testing/sysfs-platform-intel-pmc
> @@ -11,8 +11,10 @@ Description:
> to take effect.
>
> Display global reset setting bits for PMC.
> +
> * bit 31 - global reset is locked
> * bit 20 - global reset is set
> +
> Writing bit 20 value to the etr3 will induce
> a platform "global reset" upon consequent platform reset,
> in case the register is not locked.
>
