On Tue, Jul 14, 2020 at 9:22 AM David E. Box <david.e.box@xxxxxxxxxxxxxxx> wrote: > > Add PCIe DVSEC extended capability ID and defines for the header offsets. > Defined in PCIe r5.0, sec 7.9.6. > Reviewed-by: Andy Shevchenko <andy.shevchenko@xxxxxxxxx> > Signed-off-by: David E. Box <david.e.box@xxxxxxxxxxxxxxx> > Acked-by: Bjorn Helgaas <bhelgaas@xxxxxxxxxx> > --- > include/uapi/linux/pci_regs.h | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > index f9701410d3b5..09daa9f07b6b 100644 > --- a/include/uapi/linux/pci_regs.h > +++ b/include/uapi/linux/pci_regs.h > @@ -720,6 +720,7 @@ > #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */ > #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */ > #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ > +#define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */ > #define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */ > #define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */ > #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_16GT > @@ -1062,6 +1063,10 @@ > #define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */ > #define PCI_L1SS_CTL2 0x0c /* Control 2 Register */ > > +/* Designated Vendor-Specific (DVSEC, PCI_EXT_CAP_ID_DVSEC) */ > +#define PCI_DVSEC_HEADER1 0x4 /* Vendor-Specific Header1 */ > +#define PCI_DVSEC_HEADER2 0x8 /* Vendor-Specific Header2 */ > + > /* Data Link Feature */ > #define PCI_DLF_CAP 0x04 /* Capabilities Register */ > #define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */ > -- > 2.20.1 > -- With Best Regards, Andy Shevchenko
