On Tue, Apr 21, 2020 at 02:10:19PM +0530, Archana Patni wrote:
> Jasper Lake uses Icelake PCH IPs and the S0ix debug interfaces are same as
> Icelake. It uses SLP_S0_DBG register latch/read interface from Icelake
> generation. It doesn't use Tiger Lake LPM debug registers. Change the
> Jasper Lake S0ix debug interface to use the ICL reg map.
LGTM!
> Fixes: 16292bed9c ("platform/x86: intel_pmc_core: Add Atom based Jasper Lake (JSL) platform support")
> Signed-off-by: Archana Patni <archana.patni@xxxxxxxxx>
> Acked-by: David E. Box <david.e.box@xxxxxxxxx>
> Tested-by: Divagar Mohandass <divagar.mohandass@xxxxxxxxx>
> ---
> drivers/platform/x86/intel_pmc_core.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel_pmc_core.c
> index d2a5d4c..a130859 100644
> --- a/drivers/platform/x86/intel_pmc_core.c
> +++ b/drivers/platform/x86/intel_pmc_core.c
> @@ -255,7 +255,7 @@
> };
>
> static const struct pmc_bit_map icl_pfear_map[] = {
> - /* Ice Lake generation onwards only */
> + /* Ice Lake and Jasper Lake generation onwards only */
> {"RES_65", BIT(0)},
> {"RES_66", BIT(1)},
> {"RES_67", BIT(2)},
> @@ -274,7 +274,7 @@
> };
>
> static const struct pmc_bit_map tgl_pfear_map[] = {
> - /* Tiger Lake, Elkhart Lake and Jasper Lake generation onwards only */
> + /* Tiger Lake and Elkhart Lake generation onwards only */
> {"PSF9", BIT(0)},
> {"RES_66", BIT(1)},
> {"RES_67", BIT(2)},
> @@ -1156,7 +1156,7 @@ static inline void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
> X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L, &tgl_reg_map),
> X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE, &tgl_reg_map),
> X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, &tgl_reg_map),
> - X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, &tgl_reg_map),
> + X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, &icl_reg_map),
> {}
> };
>
> --
> 1.9.1
>
--
With Best Regards,
Andy Shevchenko
