> > /* Cannon Lake: PGD PFET Enable Ack Status Register(s) bitmap */
> > static const struct pmc_bit_map cnp_pfear_map[] = {
> > + /* Reserved for Cannon Lake but valid for Comet Lake */
> > {"PMC", BIT(0)},
> > {"OPI-DMI", BIT(1)},
> > {"SPI/eSPI", BIT(2)},
> > @@ -879,6 +880,8 @@ static const struct x86_cpu_id intel_pmc_core_ids[]
> = {
> > INTEL_CPU_FAM6(TIGERLAKE_L, tgl_reg_map),
> > INTEL_CPU_FAM6(TIGERLAKE, tgl_reg_map),
> > INTEL_CPU_FAM6(ATOM_TREMONT, tgl_reg_map),
> > + INTEL_CPU_FAM6(COMETLAKE, cnp_reg_map),
> > + INTEL_CPU_FAM6(COMETLAKE_L, cnp_reg_map),
> > {}
> > };
> >
>
> Just a nit, that I'm not sure if there is a policy around.
> Shouldn't the order of these reflect the actual order they're available to the
> marketplace? So CML may want to come earlier in the patch series to reflect
> that aspect.
Hi Mario, agreed! I will send this patch separately from the series as this is an urgent request from Dell.
