On Fri, Sep 27, 2019 at 9:01 AM Andy Shevchenko <andy.shevchenko@xxxxxxxxx> wrote: > On Thu, Sep 26, 2019 at 9:43 PM Gayatri Kammela > <gayatri.kammela@xxxxxxxxx> wrote: > > Thank you for the series, I'll comment them later. > > For now, check how to properly setup prefix for all patches. The Title > all broken. > On top of that the fully inconsistent SoC naming through the existing code / new additions. I'm pretty sure you need to spell platforms as Tiger Lake, Elkhart Lake and so on everywhere. Fix this, but do not send new version till I look at the code here. > > Patch 1: Cleans up termination lines > > Patch 2: Refactor driver for ease of adding new SoCs > > Patch 3: Refactor debugfs entry for PCH IPs power gating status > > Patch 4: Add Tiger Lake legacy support to pmc_core > > Patch 5: Add Elkhart Lake legacy support to pmc_core > > > > All the information regarding the PCH IPs and names of IPs will be available > > in *future* Intel's Platform Controller Hub (PCH) External Design Specification > > (EDS) document. > > When? -- With Best Regards, Andy Shevchenko
