On Tue, 2018-11-06 at 15:45 +0200, Jarkko Sakkinen wrote:
> From: Sean Christopherson <sean.j.christopherson@xxxxxxxxx>
>
> Similar to other large Intel features such as VMX and TXT, SGX must be
> explicitly enabled in IA32_FEATURE_CONTROL MSR to be truly usable.
> Clear all SGX related capabilities if SGX is not fully enabled in
> IA32_FEATURE_CONTROL or if the SGX1 instruction set isn't supported
> (impossible on bare metal, theoretically possible in a VM if the VMM is
> doing something weird).
>
> Like SGX itself, SGX Launch Control must be explicitly enabled via a
> flag in IA32_FEATURE_CONTROL. Clear the SGX_LC capability if Launch
> Control is not fully enabled (or obviously if SGX itself is disabled).
>
> Note that clearing X86_FEATURE_SGX_LC creates a bit of a conundrum
> regarding the SGXLEPUBKEYHASH MSRs, as it may be desirable to read the
> MSRs even if they are not writable, e.g. to query the configured key,
> but clearing the capability leaves no breadcrum for discerning whether
> or not the MSRs exist. But, such usage will be rare (KVM is the only
> known case at this time) and not performance critical, so it's not
> unreasonable to require the use of rdmsr_safe(). Clearing the cap bit
> eliminates the need for an additional flag to track whether or not
> Launch Control is truly enabled, which is what we care about the vast
> majority of the time.
>
> Signed-off-by: Sean Christopherson <sean.j.christopherson@xxxxxxxxx>
> Co-developed-by: Jarkko Sakkinen <jarkko.sakkinen@xxxxxxxxxxxxxxx>
> Signed-off-by: Jarkko Sakkinen <jarkko.sakkinen@xxxxxxxxxxxxxxx>
> ---
> arch/x86/kernel/cpu/intel.c | 37 +++++++++++++++++++++++++++++++++++++
> 1 file changed, 37 insertions(+)
>
> diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
> index fc3c07fe7df5..8a20a193d399 100644
> --- a/arch/x86/kernel/cpu/intel.c
> +++ b/arch/x86/kernel/cpu/intel.c
> @@ -596,6 +596,40 @@ static void detect_tme(struct cpuinfo_x86 *c)
> c->x86_phys_bits -= keyid_bits;
> }
>
> +static void detect_sgx(struct cpuinfo_x86 *c)
> +{
> + unsigned long long fc;
> +
> + rdmsrl(MSR_IA32_FEATURE_CONTROL, fc);
> + if (!(fc & FEATURE_CONTROL_LOCKED)) {
> + pr_err_once("sgx: IA32_FEATURE_CONTROL MSR is not locked\n");
> + goto out_unsupported;
> + }
> +
> + if (!(fc & FEATURE_CONTROL_SGX_ENABLE)) {
> + pr_err_once("sgx: not enabled in IA32_FEATURE_CONTROL MSR\n");
> + goto out_unsupported;
> + }
> +
> + if (!cpu_has(c, X86_FEATURE_SGX1)) {
> + pr_err_once("sgx: SGX1 instruction set not supported\n");
> + goto out_unsupported;
> + }
> +
> + if (!(fc & FEATURE_CONTROL_SGX_LE_WR)) {
FEATURE_CONTROL_SGX_LE_WR isn't added until patch 13/22. The patch
can simply be moved earlier in the series if you want to introduce
the full detect_sgx() in a single patch. The only reason SGX_LE_WR
was added later in the series was to bundle the Launch Control stuff
together.
> + pr_info_once("sgx: launch control MSRs are not writable\n");
> + goto out_msrs_rdonly;
> + }
> +
> + return;
> +out_unsupported:
> + setup_clear_cpu_cap(X86_FEATURE_SGX);
> + setup_clear_cpu_cap(X86_FEATURE_SGX1);
> + setup_clear_cpu_cap(X86_FEATURE_SGX2);
> +out_msrs_rdonly:
> + setup_clear_cpu_cap(X86_FEATURE_SGX_LC);
> +}
> +
> static void init_intel_energy_perf(struct cpuinfo_x86 *c)
> {
> u64 epb;
> @@ -763,6 +797,9 @@ static void init_intel(struct cpuinfo_x86 *c)
> if (cpu_has(c, X86_FEATURE_TME))
> detect_tme(c);
>
> + if (cpu_has(c, X86_FEATURE_SGX))
> + detect_sgx(c);
> +
> init_intel_energy_perf(c);
>
> init_intel_misc_features(c);
